"Dmitriy V'jukov" <> writes:
> On 2 อมส, 00:45, Anthony Williams <anthony_w....@yahoo.com> wrote:
>> "Dmitriy V'jukov" <dvyu...@gmail.com> writes:
>> > I am trying to figure out difference between memory_order_acq_rel and
>> > memory_order_seq_cst memory order in C++0x.
>>
>> seq_cst implies Sequential Consistency: *all* seq_cst accesses to *all*
>> variables form a single total order for any given run of the application: it
>> is as-if the threads were reduced to a direct interleaving of instructions.
>>
>> acq_rel provides *pairwise* ordering between two threads. It is possible for
>> everything to follow acq_rel semantics, and two threads see modifications to
>> two variables in different orders.
>>
>> See slides 8-12 in the presentation I did on C++0x threads at ACCU 2008:
>>
>> <http://www.justsoftwaresolutions.co.uk/threading/future-of-concurrenc...>
>>
>> > But what is memory_order_acq_rel? And when I need it? Can you provide
>> > some example?
>>
>> Sequential Consistency can impose high synchronization costs on machines with
>> many CPUs due to the requirement for a single total order. The pairwise
>> synchronization of acq_rel can be a significant performance optimization in
>> those cases.
>
>
> Ok. Thank you. So memory_order_acq_rel is what usually called "full
> fence" (mfence on x86). And memory_order_seq_cst also enforces total
> order between *all* modifications in the system (locked instruction on
> x86).
x86 is a bad architecture to use for examples, since there are too many
implicit fences, but I think you understand. I believe that the differences
are particularly apparent on architectures like PPC or alpha where
synchronization is explicit.
It is also worth noting that seq_cst only enforces a total order of seq_cst
operations: relaxed operations are still unordered, and a seq_cst operation is
treated as acq_rel by any other acquire/release/acq_rel operations.
> Hmmm... Now I am trying to figure out when memory_order_acq_rel is
> insufficient, and one need memory_order_seq_cst. I can't imagine any
> example straight off. But there must be some substantial reasons for
> inclusion memory_order_seq_cst into standard. Can you provide some
> example with memory_order_seq_cst?
seq_cst is included, and is the default, because it is easiest to reason
about. If you looked at my slides, many people will find slide 11 hard to deal
with: the two reader threads see different orders of events.
Atomic ops are hard anyway, but non-SC atomics are an order of magnitude
harder.
Anthony
--
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