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stumped on syntax yet again!

 
 
Shannon
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      05-07-2008
Ok, here is the relevant code snipits:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

HWID : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
RAM_addr : OUT UNSIGNED(9 DOWNTO 0);

TYPE reg_type IS ARRAY (0 TO NUM_REGS-1) OF
STD_LOGIC_VECTOR(HWID'RANGE);
SIGNAL regs : reg_type;
SIGNAL data_in : STD_LOGIC_VECTOR(HWID'RANGE);

Line 156: RAM_addr <= UNSIGNED("00" & data_in);

and the error is:

Error (10327): VHDL error at xFace.vhd(156): can't determine
definition of operator ""&"" -- found 2 possible definitions
Error (10647): VHDL type inferencing error at xFace.vhd(156): type of
expression is ambiguous - "reg_type" or "std_logic_vector" are two
possible matches
Error (10411): VHDL Type Conversion error at xFace.vhd(156): can't
determine type of object or expression near text or symbol "UNSIGNED"

I have no idea why it thinks "reg_type" is a possible match. It seems
very clear that RAM_addr is unsigned, "00" is SLV, and data_in is
SLV. "&" can only have one possible meaning. I'm sure that I'm doing
something else wrong that you guys will point out in less than a
second!

Shannon
 
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Mike Treseler
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      05-07-2008
Shannon wrote:

> Line 156: RAM_addr <= UNSIGNED("00" & data_in);
> and the error is:
>
> Error (10327): VHDL error at xFace.vhd(156): can't determine
> definition of operator ""&"" -- found 2 possible definitions
> Error (10647): VHDL type inferencing error at xFace.vhd(156): type of
> expression is ambiguous - "reg_type" or "std_logic_vector" are two
> possible matches
> Error (10411): VHDL Type Conversion error at xFace.vhd(156): can't
> determine type of object or expression near text or symbol "UNSIGNED"
>
> I have no idea why it thinks "reg_type" is a possible match.


Make arrays of subtypes, not base types.

The problem is inside the parens.
"00" is an anonymous type that could be an reg_type *element*.

STD_LOGIC_VECTOR(HWID'RANGE) is an anonymous subtype.

The LRM does not require the compiler to think further.
That's just the way it is.

Simplest fix is to declare and use subtypes for the
various STD_LOGIC_VECTOR widths.

-- Mike Treseler
 
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Shannon
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      05-07-2008
On May 7, 10:57*am, Mike Treseler <(E-Mail Removed)> wrote:
> Shannon wrote:
> > Line 156: *RAM_addr <= UNSIGNED("00" & data_in);
> > and the error is:

>
> > Error (10327): VHDL error at xFace.vhd(156): can't determine
> > definition of operator ""&"" -- found 2 possible definitions
> > Error (10647): VHDL type inferencing error at xFace.vhd(156): type of
> > expression is ambiguous - "reg_type" or "std_logic_vector" are two
> > possible matches
> > Error (10411): VHDL Type Conversion error at xFace.vhd(156): can't
> > determine type of object or expression near text or symbol "UNSIGNED"

>
> > I have no idea why it thinks "reg_type" is a possible match.

>
> Make arrays of subtypes, not base types.
>
> The problem is inside the parens.
> "00" is an anonymous type that could be an reg_type *element*.
>
> STD_LOGIC_VECTOR(HWID'RANGE) is an anonymous subtype.
>
> The LRM does not require the compiler to think further.
> That's just the way it is.
>
> Simplest fix is to declare and use subtypes for the
> various STD_LOGIC_VECTOR widths.
>
> * * * *-- Mike Treseler


Thanks for the help Mike. I guess I still don't understand. I tried
googling for "anonymous subtype" but I didn't find any helpful
information.

I tried declaring a subtype by doing:

subtype hwid_type IS STD_LOGIC_VECTOR(7 DOWNTO 0);

and then:

TYPE reg_type IS ARRAY (0 TO NUM_REGS-1) OF hwid_type;
SIGNAL data_in : hwid_type;

That didn't change anything so I'm obviously not understanding the
term "anonymous subtype". Any hints?

Shannon

 
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Mike Treseler
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      05-07-2008
Shannon wrote:

> That didn't change anything so I'm obviously not understanding the
> term "anonymous subtype". Any hints?



> Line 156: RAM_addr <= UNSIGNED("00" & data_in);


RAM_addr <= my_address_subtype'("00" & data_in);
 
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Nicolas Matringe
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      05-07-2008
Mike Treseler a écrit :
> Shannon wrote:
>
>> That didn't change anything so I'm obviously not understanding the
>> term "anonymous subtype". Any hints?

>
>
>> Line 156: RAM_addr <= UNSIGNED("00" & data_in);

>
> RAM_addr <= my_address_subtype'("00" & data_in);


I recently had a similar problem (though I was only using SLVs) and
fixed it by pulling the litteral constant out of the cast :

RAM_addr <= "00" & unsigned(data_in);

In this case the context is clear : "00" must be unsigned to make the
assignment valid.
I still don't understand why the context is unclear when concatenating a
litteral constant and a std_logic_vector.

Nicolas
 
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Mike Treseler
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      05-07-2008
Nicolas Matringe wrote:
>
> I recently had a similar problem (though I was only using SLVs) and
> fixed it by pulling the litteral constant out of the cast :
>
> RAM_addr <= "00" & unsigned(data_in);


Yes. Of course. That's the ticket.


> I still don't understand why the context is unclear when concatenating a
> literal constant and a std_logic_vector.


The parser is not saying that "00" won't '&' with data_in.
It's saying that it is possible that "00"
was *meant* to be an element of another type in scope.
Which would be a type error.
So it is a type error.
Hmmm.

-- Mike Treseler
 
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Shannon
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      05-07-2008
On May 7, 1:26*pm, Mike Treseler <(E-Mail Removed)> wrote:
> Nicolas Matringe wrote:
>
> > I recently had a similar problem (though I was only using SLVs) and
> > fixed it by pulling the litteral constant out of the cast :

>
> > RAM_addr <= "00" & unsigned(data_in);

>
> Yes. Of course. That's the ticket.
>
> > I still don't understand why the context is unclear when concatenating a
> > literal constant and a std_logic_vector.

>
> The parser is not saying that "00" won't '&' with data_in.
> It's saying that it is possible that "00"
> was *meant* to be an element of another type in scope.
> Which would be a type error.
> So it is a type error.
> Hmmm.
>
> * * *-- Mike Treseler


RAM_addr is of type UNSIGNED not 'my_address_subtype'
So I tried:

RAM_addr <= UNSIGNED(my_address_subtype'("00" & data_in));

but then I'm back to the original errors again.

Nicolas's solution worked although I still don't understand why my
original line is wrong.

Thanks all!

Shannon

 
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Shannon
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      05-07-2008
On May 7, 1:34*pm, Shannon <(E-Mail Removed)> wrote:
> On May 7, 1:26*pm, Mike Treseler <(E-Mail Removed)> wrote:
>
>
>
>
>
> > Nicolas Matringe wrote:

>
> > > I recently had a similar problem (though I was only using SLVs) and
> > > fixed it by pulling the litteral constant out of the cast :

>
> > > RAM_addr <= "00" & unsigned(data_in);

>
> > Yes. Of course. That's the ticket.

>
> > > I still don't understand why the context is unclear when concatenating a
> > > literal constant and a std_logic_vector.

>
> > The parser is not saying that "00" won't '&' with data_in.
> > It's saying that it is possible that "00"
> > was *meant* to be an element of another type in scope.
> > Which would be a type error.
> > So it is a type error.
> > Hmmm.

>
> > * * *-- Mike Treseler

>
> RAM_addr is of type UNSIGNED not 'my_address_subtype'
> So I tried:
>
> RAM_addr <= UNSIGNED(my_address_subtype'("00" & data_in));
>
> but then I'm back to the original errors again.
>
> Nicolas's solution worked although I still don't understand why my
> original line is wrong.
>
> Thanks all!
>
> Shannon- Hide quoted text -
>
> - Show quoted text -


If "00" is a vague type in this case why can't I cast it to make the
error go away? For example:

RAM_addr <= UNSIGNED(STD_LOGIC_VECTOR'("00") & data_in);

Shannon
 
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Mike Treseler
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      05-07-2008
Shannon wrote:

> If "00" is a vague type in this case why can't I cast it to make the
> error go away?


Declare it as a constant to give it a type.

That's good practice in any case.
I often declare zero constants for this:

RAM_addr <= my_adr_zero_c + data_in;

-- Mike Treseler
 
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Martin Thompson
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      05-08-2008
Shannon <(E-Mail Removed)> writes:

> If "00" is a vague type in this case why can't I cast it to make the
> error go away? For example:
>
> RAM_addr <= UNSIGNED(STD_LOGIC_VECTOR'("00") & data_in);
>


You should be able to, certainly I have in the past. Does it not work?

Cheers,
Martin

--
http://www.velocityreviews.com/forums/(E-Mail Removed)
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
 
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