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Ripple chain logic in VHDL

 
 
Govinda Govinda is offline
Junior Member
Join Date: Aug 2007
Posts: 7
 
      05-06-2008
Hi,

What is the best way to write a vhdl code for the following encoded logic?

If there is a 4 bit register and you only need to select the first '1' in that register starting from LSB and set all others to zero, how can that be written up in VHDL? I need to do this for a 32 bit register and I cant believe writing up the whole logic (one huge concurrent statement for each bit, especially the MSBs) is the best way to do it. Can anyone here suggest any alternatives?

eg: 1011 needs to be 0001
1100 needs to be 0100
1110 needs to be 0010 etc.


Thanks a lot- any help would be greatly appreciated.

Govinda
 
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jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      05-06-2008
Hi

Could it be a carry lookahead adder ?

Any way can you find inspiration at this page -
specially to "for-loop based" version.
http://www.jjmk.dk/MMMI/Lessons/06_A...Head/Index.htm

Your welcome
Jeppe
 
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jeppe jeppe is offline
Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 348
 
      05-06-2008
Ok try this

PHP Code:
library IEEE;
use 
IEEE.STD_LOGIC_1164.ALL;
use 
IEEE.STD_LOGIC_ARITH.ALL;
use 
IEEE.STD_LOGIC_UNSIGNED.ALL;

entity logic_test1 is
    Port 
in  std_logic_vector(5 downto 0);
           
out std_logic_vector(5 downto 0));
end logic_test1;

architecture Behavioral of logic_test1 is

begin
   process
A)
       
variable i,jinteger;
   
begin
       Y 
<= (others => '0'); 
       
:= 1;
        
:= 0;
       while 
2**5 loop
             
if A(j)='1' then
               Y 
<= Conv_std_logic_vector(i,6);
                exit;
         
end if;
            
:= 2;
            
:= 1;
        
end loop
    
end process;

end Behavioral
 
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Govinda Govinda is offline
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Join Date: Aug 2007
Posts: 7
 
      05-07-2008
Thanks a lot Jeppe
 
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