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Array initialisation in vhdl

san3885 san3885 is offline
Junior Member
Join Date: Apr 2008
Posts: 1
Hi friends....

i wanted to know whether we can initialise a vhdl array type variable or signal as shown below...
type example is array ( 1 to 10, 1 to 10 ) of any type
signal test: example;
for i is 1 to 10 loop
for j is 1 to 10 loop
test(i,j) <= "same 'array type' element"
end loop
end loop


when i tried in ISE 8.2i i got an error as test(i) is invalid array index

since im a beginner in VHDL ...u guys plz throw some light on this concept

Last edited by san3885; 04-27-2008 at 08:35 AM..
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jeppe jeppe is offline
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Join Date: Mar 2008
Location: Denmark
Posts: 348
would i and j be variables of the type integer?
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