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securing VHDL source code

sridar sridar is offline
Join Date: Jun 2007
Posts: 52
Hi friendz,

In xilinx ISE, Can i encapsulate VHDL source code in such a way that my team member need not (he shouldn't) to access my source code,but he should be able to use my code in his design by instantiating it as a component. Is it possible or would u prefer any other method.
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