Variable scope

Hi,

I'm writing a VHDL program consisting of multiple entities, using multiple packages that sometimes contain equal signal names.

So, I must hide the declared signals from each other:

architecture behavioural of entity1 is
use work.mypackage1.all;
begin
..
end package;

architecture behavioural of entity2 is
use work.mypackage2.all;
begin
..
end package;

This doesnt work when compiling in Xilinx (it says the required filenames that should be known from the package cannot be recognized in the architecture) Is it impossible to use packages there? Some VHDL texts I've read say it well is possible..


Yea, I know the cheap way would be to just put the signals there instead of including them by a package, but I'd like to make it work with packages.


Addendum:
Another possibility I've tried is just adding variable declarations in each source file before the entity, at the beginning of the file (each of my source files only contains one entity and one architecture). This compiles fine in ModelSim (scope of a package maybe only valid to the entity directly following the declaration). However, this fails when I try to do this in Xilinx ISE because such package inclusions are treated as global.

toller

[toller]

Disregard this post, will repost in VHDL newsgroup. Sorry..

toller