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For those that missed this one:

OptNgn today announced that it is offering a floating point VHDL library
under the GPLv3 Open Source License. FPGA designers can now save months of
coding and debug time by using these floating point libraries instead of
creating the VHDL from scratch. The parameterized floating point operators
being introduced are in three groups: Arithmetic, Transcendental and
Trigonometric......

http://www10.edacafe.com/nbc/article...9106&page_no=2

Download source files from here:

http://sourceforge.net/projects/libhdlfltp

Hans
www.ht-lab.com

HT-Lab wrote:

> http://sourceforge.net/projects/libhdlfltp

Interesting.
Thanks for the link.
Too bad the author chose not to use the standard packages.

See also:
http://www.vhdl.org/vhdl-200x/vhdl-2...ges/files.html

-- Mike Treseler

On Apr 17, 1:41 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
> HT-Lab wrote:
> >http://sourceforge.net/projects/libhdlfltp
>
> Interesting.
> Thanks for the link.
> Too bad the author chose not to use the standard packages.
>
> See also:http://www.vhdl.org/vhdl-200x/vhdl-2...ges/files.html
>
> -- Mike Treseler

Mike,

We originally had the IEEE candidate library by David Bishop you link
to above
as a wrapper around the core floating point elements currently in
libhdlfltp,
as it is well constructed and has very nice conversion functions.

The wrapper was removed from the release due to two problems.

1. Xilinx does not currently support negative indices, so you can't
synthesize
anything involving these components in ISE or Webpack.
You can with some of the other vendors.

2. There are IEEE licensing problems in that a user would need to buy
the to-be-ratified floating/fixed point spec from the IEEE
in order for the source code to be legally available,
which is a major problem for synthesis, as you need the source
code to synthesize.

This is also currently the case for the real math library,
but since that library is only for simulation,
the vendors get around that by shipping compiled models with their
products.
If you legally want the source code to that package, you must also
first purchase
the actual spec from the IEEE.

When these two problems are solved, we see putting the IEEE package as
a wrapper
around the the core elements of libhdlfltp. In fact, as a GPL'ed
project,
anyone is welcome to participate in that work!

alan

ajjc wrote:

> The wrapper was removed from the release due to two problems.
> 1. Xilinx does not currently support negative indices, so you can't
> synthesize
> anything involving these components in ISE or Webpack.

I use quartus. It works fine.

> 2. There are IEEE licensing problems in that a user would need to buy
> the to-be-ratified floating/fixed point spec from the IEEE
> in order for the source code to be legally available,
> which is a major problem for synthesis, as you need the source
> code to synthesize.

It's ok to call the functions and publish your own code.
I'd leave the rest up to the user.

-- Mike

[gzidude]

You guys are my HEROS!!!!!

"ajjc" <> wrote in message
news:5099c9f8-2320-41a7-bfb6-...
> On Apr 17, 1:41 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
...
> When these two problems are solved, we see putting the IEEE package as
> a wrapper
> around the the core elements of libhdlfltp. In fact, as a GPL'ed
> project,
> anyone is welcome to participate in that work!
>
> alan
>

Thanks for making this package freely available!

Hans
www.ht-lab.com



>

On Apr 20, 5:06 pm, David Bishop <dbis...@vhdl.org> wrote:
> ajjc wrote:
> > We originally had the IEEE candidate library by David Bishop you link
> > to above
> > as a wrapper around the core floating point elements currently in
> > libhdlfltp,
> > as it is well constructed and has very nice conversion functions.
>
> > The wrapper was removed from the release due to two problems.
>
> > 1. Xilinx does not currently support negative indices, so you can't
> > synthesize
> > anything involving these components in ISE or Webpack.
> > You can with some of the other vendors.
>
> I've gotten parts of the package to work in the latest release (9.0)
> I've been promised full support by 11.0. Altera and Synplicity will
> use them without modification. Synopsys needs a new tweeks in the
> code, but it runs in the 2007.12 release.
>
Sounds good!...they are on release 10.1, so in their next major
release,
there will be the possibility of major vendor convergence on fixed
and floating point
support combining, through wrappers, both vhdl and verilog support.

> > 2. There are IEEE licensing problems in that a user would need to buy
> > the to-be-ratified floating/fixed point spec from the IEEE
> > in order for the source code to be legally available,
> > which is a major problem for synthesis, as you need the source
> > code to synthesize.
>
> The VHDL-93 versions of the packages had the IEEE copyright removed from
> them for just that reason. Those you can use free of any liability
> issues. You will find them at:http://www.vhdl.org/fphdl/vhdl.html
>

Ok, thanks! I believe that they currently have no license on them,
which is fine for individual use, but gives no rules for any type
of distribution or other usage.

> > This is also currently the case for the real math library,
> > but since that library is only for simulation,
> > the vendors get around that by shipping compiled models with their
> > products.
> > If you legally want the source code to that package, you must also
> > first purchase
> > the actual spec from the IEEE.
>
> We are working on that with the IEEE on that. It has been an uphill issue.
>

I understand. I attended a few of the meetings by phone.

> > When these two problems are solved, we see putting the IEEE package as
> > a wrapper
> > around the the core elements of libhdlfltp. In fact, as a GPL'ed
> > project,
> > anyone is welcome to participate in that work!
>
> I like the idea of the GPL license. I wonder if I could put that on
> the VHDL-93 versions to keep the IEEE hands off of them.

I would recommend LGPLv3, as that will lead to the most ubiquitous
usage,
while still being compatible with any version of GPL.
This is not as pure,
in the Richard Stallman sense of use, as strict GPL would be,
but will allow your library to become
a GPL firewall interface to other libraries.
Remember, IANAL (I Am Not A Lawyer), so check with your own counsel
for legal advice.

alan

[master_DMFC]

hello,

i'm using Quartus II version 6.0 to develop some VHDL and now i need to use this library but i'm experiencing some problems because when i try to run i get an error message saying that the design library does not contain primary unit. and i don't know why...

can you please explain me how you did to make it work??


Thank you,
Duarte Carona






"Error (10481): VHDL Use Clause error at qam_modulator.vhd(53): design library "pkg_sqrt" does not contain primary unit "fpsqrt_sqrt""

Originally Posted by Mike Treseler

ajjc wrote:

> The wrapper was removed from the release due to two problems.
> 1. Xilinx does not currently support negative indices, so you can't
> synthesize
> anything involving these components in ISE or Webpack.

I use quartus. It works fine.

> 2. There are IEEE licensing problems in that a user would need to buy
> the to-be-ratified floating/fixed point spec from the IEEE
> in order for the source code to be legally available,
> which is a major problem for synthesis, as you need the source
> code to synthesize.

It's ok to call the functions and publish your own code.
I'd leave the rest up to the user.

-- Mike