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VHDL, arbitrary string length

 
 
eko eko is offline
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Join Date: Apr 2008
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      04-16-2008
Hi,

for a testbench I need a procedure loading arbitrary files with stimuli data. Now my problem is vhdl wants me to define the string length of the file name+path in advance. But since this TB is used for huge amount of testcases run in several different environments I cannot tell the length of the file name strings before the procedure is called...

Further a quite similar problem arises when I read the stimuli files, since they contain signal names and their values, I cannot tell in advance how big the string read from a line will be...how can I just read a string of arbitrary length from a file with an arbitrary name?

Anyone having an idea how to solve this?

Thanks!
 

Last edited by eko; 04-16-2008 at 04:11 PM..
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scottcarl scottcarl is offline
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Join Date: May 2007
Location: USA
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      04-16-2008
VHDL is not very forgiving it its language format. If you truely don't know the input format of the data then I highly suggest that you use some other software program, c-shell, python, ... etc, to format the data into a known state. Otherwise you'll just end up getting lots of errors during simulation that will drive you nuts.
You could try reading in a very large string (1 to 120) perhaps. Then you'll have to check the first letters, numbers, or characters to determine if the input string is valid data, comments, blank line, or something else. There is also a package out there called iopakb.vhd and iopakp.vhd (Google it) that has a c-type "fscan" function that will read in strings very well. However you try to do it there is no simple answer when your input data is of a random nature. You'll have to put in a ton of 'checking' logic as long as the input is of a somewhat unknown form.

Scott C
 
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eko eko is offline
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      04-17-2008
Thank you, that was exactly what i was looking for I used this some time ago but somehow had forgotten about std_iopak...
 
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prasanthri prasanthri is offline
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      05-29-2008
hi,
i would like to drive a vhdl testbench with commands reading from a file.the expected command format is like" module activity values", 'activity' indicates what to be done on the specified 'module' for testing and 'values' specifies what all parameters have to be used for that 'activity'.

for example:writing to a memory-

"memory write 0x0001|0001,0x0002|0010,0x0003|0011"

how can i read these commands from the file in correct order and run my test bench.
 
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