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Latch problem in FSM

engrjet engrjet is offline
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Join Date: Jan 2008
Posts: 4
I'm facing a problem in latching data inside the state of an FSM.
If I latch it in any of the state and read it out side the process I read it wrongly but if I directly latch it out side the process I read it correctly.
what may be the reason. what will be the solution for this???

please reply
Thank You
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jeppe jeppe is offline
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Join Date: Mar 2008
Location: Denmark
Posts: 348
Try Evita VHDL handbook from Aldec.Com specially chapter 6

Last edited by jeppe; 03-13-2008 at 07:38 AM..
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