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03-12-2008, 06:48 PM
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#1 |
Latch problem in FSM
Hi
I'm facing a problem in latching data inside the state of an FSM. If I latch it in any of the state and read it out side the process I read it wrongly but if I directly latch it out side the process I read it correctly. what may be the reason. what will be the solution for this??? please reply Thank You engrjet |
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03-13-2008, 07:35 AM
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#2 |
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Senior Member
Join Date: Mar 2008
Location: Denmark
Posts: 245
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Try Evita VHDL handbook from Aldec.Com specially chapter 6
jeppe Last edited by jeppe : 03-13-2008 at 07:38 AM. |
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