Buffer

Hi everyone
i want to model a buffer by VHDL

i have a series of assign statemnet which assign the output of the
gates to diffrent signals,
here is couple lines of what i have.
msti(i).hgrant <= hgrant(i);
msti(i).hready <= hready;
msti(i).hrdata <= hrdata;
msti(i).hresp <= hresp; ,

it's working verywell by itself, but i need to synthesis it, and
after synthesising i get error on them , and need a buffer to store
the output and then assign the the value to to the right hand signals.

how can i add the buffer?
thank you

shohreh@gmail.com

[jeppe]

I'm not sure where your problem origin. Could it be use of a record structure - never tried that for synthesize.

You should be aware that signals might "disappear" if the synthesize tools finds they are not needed.

Consider this example:

Entity .....
Port( Clk: IN Std_Logic;
Count OUT Std_logic_vector( 3 downto 0)
);

Architecture ......

begin
process( Clk)
begin
if rising_edge( Clk) then
Count <= Count + 1; -- THIS LINE GIVES AN ERROR
end if;
end process;
end ...

----------------------------------------------------------------
Entity .....
Port( Clk: IN Std_Logic;
Count INOUT Std_logic_vector( 3 downto 0)
);

Architecture ......

begin
process( Clk)
begin
if rising_edge( Clk) then
Count <= Count + 1; -- OK WITH INOUT
end if;
end process;
end ...

----------------------------------------------------------------
Entity .....
Port( Clk: IN Std_Logic;
Count OUT Std_logic_vector( 3 downto 0)
);

Architecture ......
Signal Temp_Count: Std_logic_vector( 3 downto 0)

begin
Count <= Temp_Count;
process( Clk)
begin
if rising_edge( Clk) then
Temp_Count <= Temp_Count + 1; --OK
end if;
end process;
end ...

Jeppe

jeppe

On Mar 11, 2:11*am, shoh...@gmail.com wrote:
> Hi everyone
> i want to model a buffer by VHDL
>
> i have a series of assign statemnet which assign the output of the
> gates to diffrent signals,
> here is couple lines of what i have.
> msti(i).hgrant *<= hgrant(i);
> msti(i).hready *<= hready;
> msti(i).hrdata *<= hrdata;
> msti(i).hresp * <= hresp; ,
>
> *it's working verywell by itself, but i need to synthesis it, and
> after synthesising i get error on them

What error is actually getting reported?

> , and need a buffer to store
> the output

Says who?

> and then assign the the value to to the right hand signals.
>

Assign the value of what to the right hand signals?

> how can i add the buffer?

The statements that you posted are examples of 'buffers'. It doesn't
appear to me that you've posted enough of your code for anyone to
figure what the real problem is and by not posting what the error
message is you've made it even more difficult. You then seem to leap
to the conclusion that you need a 'buffer' for some reason without
even realizing that each of your concurrent assignments are examples
of adding such a buffer.

More information would help.

Kevin Jennings

KJ

IF you want quality help, you need to give us more information.

What is the ERROR message? Why do you believe you need a buffer?
Why do yuou believe your code works prior to synthesis? etc....

<> wrote in message
news:c4ec3da7-7da4-4ab4-b11b-...
> Hi everyone
> i want to model a buffer by VHDL
>
> i have a series of assign statemnet which assign the output of the
> gates to diffrent signals,
> here is couple lines of what i have.
> msti(i).hgrant <= hgrant(i);
> msti(i).hready <= hready;
> msti(i).hrdata <= hrdata;
> msti(i).hresp <= hresp; ,
>
> it's working verywell by itself, but i need to synthesis it, and
> after synthesising i get error on them , and need a buffer to store
> the output and then assign the the value to to the right hand signals.
>
> how can i add the buffer?
> thank you

Dwayne Dilbeck