Cannot Infer Wired-Or in Leonardo Spectrum

Hello,
I have been trying to insert some manual test points in a design for
my DFT(Design for Test) labs. What I am doing is that I am trying to
do a wired-or of the new PIs (Primary Inputs) with the node lines
which I want to have control over.

First is this the way to go about it? (i.e. a wired-or or a wired-and
solution? Can you suggest me some better ways to do that..?) If you
had experience with DFT then perhaps you could give me a tip or two as
to how should I go about it.

Secondly I cannot get the synthesis tool (leonardo spectrum) to infer
that wired-or for me. I am trying to generate an EDIF file for an ASIC
and not an FPGA so you know.

What it does is that it leaves the new inputs disconnected and they
are floating thereby decreasing the overall fault coverage (as I now
have some floating nodes that weren't there before).

Here are my source files:

- - I define my packages containing the resolution function here

library IEEE;
use IEEE.std_logic_1164.all;
use work.all;

package wired_fucns is

type std_ulogic_array is array(integer range <>) of std_ulogic;
function wired_or (drivers : in std_ulogic_array) return std_ulogic;
subtype resolved_or is wired_or std_ulogic;

end wired_fucns;


package body wired_fucns is

function wired_or (drivers : in std_ulogic_array) return std_ulogic
is

variable result : std_ulogic := '0';

begin
for index in drivers'range loop
if drivers(index) = '1' then
result := '1';
exit;
elsif drivers(index) = 'X' then
result := 'X';
end if;
end loop;
return result;
end wired_or;

end wired_fucns;

- - I use those functions in here:

library IEEE;
library work;
use work.wired_fucns.all;
use IEEE.std_logic_1164.all;

ENTITY s27_bench IS
PORT (
INP: in std_ulogic_vector(0 to 3);
OUTP : out std_ulogic_vector(0 to 0);
H : in std_ulogic;
TI : in std_ulogic_vector(0 to 2);
Tout : inout std_logic_vector(0 to 2)
);
END s27_bench ;



ARCHITECTURE structural OF s27_bench IS

component andg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component org
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component xorg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component xnorg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component nandg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component norg
generic (tpd_hl : time;
tpd_lh : time);
port (in1, in2 : std_logic;
out1 : out std_logic);
end component;

component invg
generic (tpd_hl : time;
tpd_lh : time);
port (in1 : std_logic;
out1 : out std_logic);
end component;

component buffg
generic (tpd_hl : time;
tpd_lh : time);
port (in1 : std_logic;
out1 : out std_logic);
end component;

-- ******* Portes generiques sur le nombre d'entr'e

component andg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time);
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component nandg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time );
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component org_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component norg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component xorg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component xnorg_n
generic (n : integer ;
tpd_hl : time ;
tpd_lh : time) ;
port (inp : std_logic_vector(0 to n-1);
out1 : out std_logic) ;
end component;

component DFFC
generic (tpd_hl : time;
tpd_lh : time);
port (DFFC,H,C : std_logic;
Q : out std_logic);
end component;

component DFF
generic (tpd_hl : time;
tpd_lh : time);
port (D,H : std_logic;
Q : out std_logic);
end component;

component TFFC
generic (tpd_hl : time;
tpd_lh : time);
port (T,H,C : std_logic;
Q : out std_logic);
end component;

signal INTERP : std_ulogic_vector(0 to 11):=(others=>'0') ;
signal OUTPI : std_ulogic_vector(OUTP'range):=(others=>'0') ;
signal resolved0 : resolved_or;
signal resolved1 : resolved_or;
signal resolved2 : resolved_or;

BEGIN
DFF0 : DFF generic map (1 ns,1 ns)
port map (
D => INTERP(1),
H => H,
Q => INTERP(0)); -- input to 2nd wired-or

resolved1 <= INTERP(0); -- 2nd wired-or
resolved1 <= TI(1);

DFF1 : DFF generic map (1 ns,1 ns)
port map (
-- D => INTERP(3),
D => resolved2,
H => H,
Q => INTERP(2));

resolved2 <= INTERP(3);
resolved2 <= TI(2);

DFF2 : DFF generic map (1 ns,1 ns)
port map (
D => INTERP(5),
H => H,
Q => INTERP(4));

INV0 : INVG generic map (1 ns,1 ns)
port map (
in1 => INP(0),
out1 => INTERP(6));

INV1 : INVG generic map (1 ns,1 ns)
port map (
in1 => INTERP(3),
out1 => OUTPI(0));

AND0 : ANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(6),
inp(1) => INTERP(2),
out1 => INTERP(7));

OR0 : ORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(9),
inp(1) => INTERP(7),
out1 => INTERP(); --one of the inputs to the
wired-or

resolved0 <= INTERP(; -- 1st wired-or
resolved0 <= TI(0);

OR1 : ORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(3),
inp(1) => INTERP(7),
out1 => INTERP(10));

NAND0 : NANDG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(10),
-- inp(1) => INTERP(,
inp(1) => resolved0, --output 0 of the wired-or
out1 => INTERP(11));

NOR0 : NORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INTERP(6),
inp(1) => INTERP(3),
out1 => INTERP(1));

NOR1 : NORG_N generic map (2,1 ns,1 ns)
port map (
-- inp(0) => INTERP(0),
inp(0) => resolved1,
inp(1) => INTERP(11),
out1 => INTERP(3));

NOR2 : NORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(1),
inp(1) => INTERP(4),
out1 => INTERP(9));

NOR3 : NORG_N generic map (2,1 ns,1 ns)
port map (
inp(0) => INP(2),
inp(1) => INTERP(9),
out1 => INTERP(5));

BUFFER_OUT : OUTP <= OUTPI;

Tout(0) <= INTERP(9);
Tout(1) <= INTERP(11);
Tout(2) <= INTERP(3);

END structural ;

ARCHITECTURE rtl OF s27_bench IS
signal INTERP : std_ulogic_vector(0 to 11):=(others=>'0') ;
signal OUTPI : std_ulogic_vector(OUTP'range):=(others=>'0') ;
BEGIN
REGVECT : BLOCK (H='1' AND NOT H'STABLE)
BEGIN
DFF3 : INTERP(0) <= GUARDED INTERP(1) after 1 ns;
DFF4 : INTERP(2) <= GUARDED INTERP(3) after 1 ns;
DFF5 : INTERP(4) <= GUARDED INTERP(5) after 1 ns;
END BLOCK ;
INV2 : INTERP(6) <= NOT(INP(0)) after 1 ns;
INV3 : OUTPI(0) <= NOT(INTERP(3)) after 1 ns;
AND1 : INTERP(7) <= INTERP(6) AND INTERP(2) after 1 ns;
OR2 : INTERP( <= INTERP(9) OR INTERP(7) after 1 ns;
OR3 : INTERP(10) <= INP(3) OR INTERP(7) after 1 ns;
NAND1 : INTERP(11) <= NOT(INTERP(10) AND INTERP() after 1 ns;
NOR4 : INTERP(1) <= NOT(INTERP(6) OR INTERP(3)) after 1 ns;
NOR5 : INTERP(3) <= NOT(INTERP(0) OR INTERP(11)) after 1 ns;
NOR6 : INTERP(9) <= NOT(INP(1) OR INTERP(4)) after 1 ns;
NOR7 : INTERP(5) <= NOT(INP(2) OR INTERP(9)) after 1 ns;
BUFFER_OUT : OUTP <= OUTPI;

END rtl ;

Any kind of input would be highly welcome.

Guy_Sweden

Guy_Sweden wrote:

> I have been trying to insert some manual test points in a design for
> my DFT(Design for Test) labs. What I am doing is that I am trying to
> do a wired-or of the new PIs (Primary Inputs) with the node lines
> which I want to have control over.
>
> First is this the way to go about it? (i.e. a wired-or or a wired-and
> solution?

Probably not. Does the asic library even have a tri-state buffer?
Does leo support the asic library?
If I really needed test points, I would bring out regular outputs.

> Can you suggest me some better ways to do that..?)

Insert boundary scan and redo your functional
simulations and static timing.
Check with the asic vendor for their requirements

> If you
> had experience with DFT then perhaps you could give me a tip or two as
> to how should I go about it.

I would verify the vhdl design using simulation and static timing.
I would use boundary scan for a smoke test and pin shorts/opens.
I would do system test system on the board using the real inputs and
outputs.

> Any kind of input would be highly welcome.

This response meets that standard

-- Mike Treseler

Mike Treseler

"Guy_Sweden" <> wrote in message news:b7725bd8-6dce-4be2-9ffb-...
> Hello,
> I have been trying to insert some manual test points in a design for
> my DFT(Design for Test) labs. What I am doing is that I am trying to
> do a wired-or of the new PIs (Primary Inputs) with the node lines
> which I want to have control over.
>
> First is this the way to go about it? (i.e. a wired-or or a wired-and
> solution? Can you suggest me some better ways to do that..?) If you
> had experience with DFT then perhaps you could give me a tip or two as
> to how should I go about it.
>
> Secondly I cannot get the synthesis tool (leonardo spectrum) to infer
> that wired-or for me. I am trying to generate an EDIF file for an ASIC
> and not an FPGA so you know.
>
> What it does is that it leaves the new inputs disconnected and they
> are floating thereby decreasing the overall fault coverage (as I now
> have some floating nodes that weren't there before).
>
> Here are my source files:
>
> - - I define my packages containing the resolution function here
>
> library IEEE;
> use IEEE.std_logic_1164.all;
> use work.all;
>
> package wired_fucns is
>
> type std_ulogic_array is array(integer range <>) of std_ulogic;
> function wired_or (drivers : in std_ulogic_array) return std_ulogic;
> subtype resolved_or is wired_or std_ulogic;
>
> end wired_fucns;
>
>
> package body wired_fucns is
>
> function wired_or (drivers : in std_ulogic_array) return std_ulogic
> is
>
> variable result : std_ulogic := '0';
>
> begin
> for index in drivers'range loop
> if drivers(index) = '1' then
> result := '1';
> exit;
> elsif drivers(index) = 'X' then
> result := 'X';
> end if;
> end loop;
> return result;
> end wired_or;
>
> end wired_fucns;
>

Leonardo does support user-defined resolution functions (and is the only synthesis tool that does that without synthesis pragmas),
but without a synthesis pragma it does not know that you want to a 'wired-or' for the implementation. It only knows that you want an
'or' of the drivers. Please confirm that/it that is what you see in the synthesis result.

But even with a wired_or pragma, I doubt that you get a wired-or for the resolved drivers. A reduction-or boolean operation is
probably the chosen implementation.
If you want a wired-or, then find the wired-or gate that you want in the target technology library, and instantiate it directly.
That begs the question : why do you want a wired-or for this design ? Isn't a normal reduction-or good enough ?

Rob

Rob Dekker