Re: Bit-wise Manipulation giving warnings in Synthesis

Hi,

I'm writing a state machine for a control path for a hardware neural
network implementation. I'm using Xilinx ISE 8.2i.

I have a variable "result". This variable is manipulated bit-wise
(i.e. single bits at specified indices are set and cleared as the
state machine is running). Here are the lines involving the variable:

variable result : SIGNED(31 downto 0);

uCURRENT_OUT <= STD_LOGIC_VECTOR(result);
result := (others=> '0');
result(TO_INTEGER(i)) := '1';
result(TO_INTEGER(i)) := '0';

if(STD_LOGIC_VECTOR(result) = uPrev_IN) then
NS <= S11;

When I sythesise this in Xilinx, the synthesis is successful, but
gives warnings. The warning is:

"WARNING:Xst:737 - Found 1-bit latch for signal <result_1>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the
data and gate enable inputs of this latch share common terms. This
situation will potentially lead to setup/hold violations and, as a
result, to simulation problems. This situation may come from an
incomplete case statement (all selector values are not covered). You
should carefully review if it was in your intentions to describe such
a latch."

It gives a large number of these warnings, all very similar, but with
<result_4>, <result_27>, <result_28> etc. I have checked and I dont
have any incomplete case statements.

I am anxious to solve this issue. Can anyone help me with this?

Thanks,

Mike

Moikel

Moikel wrote:

> When I sythesise this in Xilinx, the synthesis is successful, but
> gives warnings. The warning is:
>
> "WARNING:Xst:737 - Found 1-bit latch for signal <result_1>.

Synthesis completes without error, but it made
an unexpected latch, so your design intent
has not been properly described.

Consider basing your design on a synchronous template.
That rules out latches.
Debug your design using the rtl viewer
and a simulator. Good luck.

-- Mike Treseler

Mike Treseler

Assuming the order you wrote the applicable lines is the order they appear
in the code, then the first value of result is based on the previous pass,
when result was assigned values. Hence, a latch.

You haven't provided the sensitivity list, or conditions, so this is just a
guess; but then, since the tool inferred a latch, this must not be in a
typical clocked process.

JTW

"Moikel" <> wrote in message
news:664fe0ea-d671-4792-ab3f-...
> Hi,
>
> I'm writing a state machine for a control path for a hardware neural
> network implementation. I'm using Xilinx ISE 8.2i.
>
> I have a variable "result". This variable is manipulated bit-wise
> (i.e. single bits at specified indices are set and cleared as the
> state machine is running). Here are the lines involving the variable:
>
> variable result : SIGNED(31 downto 0);
>
> uCURRENT_OUT <= STD_LOGIC_VECTOR(result);
> result := (others=> '0');
> result(TO_INTEGER(i)) := '1';
> result(TO_INTEGER(i)) := '0';
>
> if(STD_LOGIC_VECTOR(result) = uPrev_IN) then
> NS <= S11;
>
> When I sythesise this in Xilinx, the synthesis is successful, but
> gives warnings. The warning is:
>
> "WARNING:Xst:737 - Found 1-bit latch for signal <result_1>.
> INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the
> data and gate enable inputs of this latch share common terms. This
> situation will potentially lead to setup/hold violations and, as a
> result, to simulation problems. This situation may come from an
> incomplete case statement (all selector values are not covered). You
> should carefully review if it was in your intentions to describe such
> a latch."
>
> It gives a large number of these warnings, all very similar, but with
> <result_4>, <result_27>, <result_28> etc. I have checked and I dont
> have any incomplete case statements.
>
> I am anxious to solve this issue. Can anyone help me with this?
>
> Thanks,
>
> Mike

jtw