Need help on LPM_ROM (Altera)

Hi group,

I want to simulate VGA signals using VHDL and still working on a code
but currently I'm confused about LPM_ROM.


Now, in order to show a character I'm using an MIF file which is
assigned to LPM_ROM megafunction. Now, the thing I do NOT understand
is how does the LPM_ROM works?

LPM_ROM has some parameters that I have assigned required values to it
but it also has inputs and output as well. In the following LPM_ROM
what should be assigned to the address? (marked with ???)

instance_of_mf : lpm_rom

GENERIC MAP (
LPM_WIDTH => 3,
LPM_WIDTHAD => 10,
LPM_NUMWORDS => 1024,
LPM_FILE => "single_character.mif",
LPM_ADDRESS_CONTROL=> "REGISTERED",
LPM_OUTDATA => "REGISTERED",
LPM_HINT => "REGISTERED",
LPM_TYPE => "REGISTERED",
INTENDED_DEVICE_FAMILY => "REGISTERED"
)
PORT MAP (
address => ????,
inclock => clk25Mhz,
outclock => clk25Mhz,
q => q

Amit

On Mar 6, 6:38 am, Amit <amit.ko...@gmail.com> wrote:
> Hi group,
>
> I want to simulate VGA signals using VHDL and still working on a code
> but currently I'm confused about LPM_ROM.
>
> Now, in order to show a character I'm using an MIF file which is
> assigned to LPM_ROM megafunction. Now, the thing I do NOT understand
> is how does the LPM_ROM works?
>
> LPM_ROM has some parameters that I have assigned required values to it
> but it also has inputs and output as well. In the following LPM_ROM
> what should be assigned to the address? (marked with ???)
>
> instance_of_mf : lpm_rom
>
> GENERIC MAP (
> LPM_WIDTH => 3,
> LPM_WIDTHAD => 10,
> LPM_NUMWORDS => 1024,
> LPM_FILE => "single_character.mif",
> LPM_ADDRESS_CONTROL=> "REGISTERED",
> LPM_OUTDATA => "REGISTERED",
> LPM_HINT => "REGISTERED",
> LPM_TYPE => "REGISTERED",
> INTENDED_DEVICE_FAMILY => "REGISTERED"
> )
> PORT MAP (
> address => ????,
> inclock => clk25Mhz,
> outclock => clk25Mhz,
> q => q

The address will need to be a 10 bit signal to select which 3 bit word
you want to read out of the memory. This rom you have set up has 1024
words that are 3 bits long. You can only read 1 at a time.

I suggest you go an read up about memory and how it works.

Tricky

On Mar 6, 2:02*am, Tricky <Trickyh...@gmail.com> wrote:
> On Mar 6, 6:38 am, Amit <amit.ko...@gmail.com> wrote:
>
>
>
>
>
> > Hi group,
>
> > *I want to simulate VGA signals using VHDL and still working on a code
> > but currently I'm confused about LPM_ROM.
>
> > Now, in order to show a character I'm using an MIF file which is
> > assigned to LPM_ROM megafunction. Now, the thing I do NOT understand
> > is how does the LPM_ROM works?
>
> > LPM_ROM has some parameters that I have assigned required values to it
> > but it also has inputs and output as well. In the following LPM_ROM
> > what should be assigned to the address? (marked with ???)
>
> > instance_of_mf : lpm_rom
>
> > GENERIC MAP (
> > LPM_WIDTH * * * * * * * => 3,
> > LPM_WIDTHAD * * * * *=> 10,
> > LPM_NUMWORDS * * => 1024,
> > LPM_FILE * * * * * * * * *=> "single_character.mif",
> > LPM_ADDRESS_CONTROL=> "REGISTERED",
> > LPM_OUTDATA * * * * => "REGISTERED",
> > LPM_HINT * * * * * * * * => "REGISTERED",
> > LPM_TYPE * * * * * * * *=> "REGISTERED",
> > INTENDED_DEVICE_FAMILY => "REGISTERED"
> > * * * * * )
> > PORT MAP (
> > address => ????,
> > inclock => clk25Mhz,
> > outclock => clk25Mhz,
> > q => q
>
> The address will need to be a 10 bit signal to select which 3 bit word
> you want to read out of the memory. This rom you have set up has 1024
> words that are 3 bits long. You can only read 1 at a time.
>
> I suggest you go an read up about memory and how it works.- Hide quoted text -
>
> - Show quoted text -

Hi Tricky,

Thanks for your response. Just to make it clear please know there are
two entities. "entity 1" will be embedded into the 2nd one. I'm using
LPM_ROM in the architecture of the 2nd. The problem is that I don't
see any address to map it to LPM_ROM address input.

where does the address come to get mapped to address argument of the
mega function?!

any advice is appreciated.


entity 1:
clock in std_logic
hsync and vsync out std_logic
pixel_row std_logic_vector(8 downto 0)
pixel_col std_logic_vector(9 downto 0 )

entity 2:
clock in std_logic
hsync out std_logic
vsync out std_logic
rgb out std_logic_vector(2 downto 0)
clk25 out std_logic and
Blank_n out std_logic

Amit

Amit wrote:

> where does the address come to get mapped to address argument of the
> mega function?!

The address is something *you* have to supply from your vga controller.

A vga controller is little more than a handful of counters. The sync
signals are generated when the counters are within a certain range.

There's at least 2 steps involved in displaying text characters on a video
screen.

1. You compute a (text) screen memory address based on the H & V counters
output from your VGA controller, depending on your chosen sceen dimensions
and resolution.
This address is used to read a character code from video RAM. The
simplest solution would use dual-port RAM for video memory.

2. You compute a character ROM address based on the character code and
(possibly) the H & V counters output from your VGA controller.
This address is used to read a pixel value from character ROM.

When you start adding colour information, a 3rd step involves using the
abovementioned pixel value in a palette table lookup.

These operations have to be pipelined, so you need to take that into
account when you sync the final pixel value with the H/VSYNC signals - ie.
you need to delay them by a few clocks.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Mark McDougall

On Mar 6, 7:00 pm, Mark McDougall <ma...@vl.com.au> wrote:
> Amit wrote:
> > where does the address come to get mapped to address argument of the
> > mega function?!
>
> The address is something *you* have to supply from your vga controller.
>
> A vga controller is little more than a handful of counters. The sync
> signals are generated when the counters are within a certain range.
>
> There's at least 2 steps involved in displaying text characters on a video
> screen.
>
> 1. You compute a (text) screen memory address based on the H & V counters
> output from your VGA controller, depending on your chosen sceen dimensions
> and resolution.
> This address is used to read a character code from video RAM. The
> simplest solution would use dual-port RAM for video memory.
>
> 2. You compute a character ROM address based on the character code and
> (possibly) the H & V counters output from your VGA controller.
> This address is used to read a pixel value from character ROM.
>
> When you start adding colour information, a 3rd step involves using the
> abovementioned pixel value in a palette table lookup.
>
> These operations have to be pipelined, so you need to take that into
> account when you sync the final pixel value with the H/VSYNC signals - ie.
> you need to delay them by a few clocks.
>
> Regards,
>
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266


Thank you Mark for the details.

Regards,
Amit

ramsin