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VHDL - ModelSim PE (student ed.) vs. Xilinx ISE Simulator

 
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Old 03-04-2008, 12:16 PM   #1
Default ModelSim PE (student ed.) vs. Xilinx ISE Simulator


Hi!

I have a synchronous design for Xilinx Spartan-3E FPGA and I'm comparing
simulation results. For Behav. sim. everything is the same. For post-map
simulation on ModelSim I get expected results. Problem is with
post-place&route simulation.

I'm asking myself which tool should I use?
Is it 'enough' to 'trust' Xilinx ISE Simulator?

Tools are installed with newest versions available & I've chose products
which I get for free.

For post-place&route simulation on Xilinx ISE Simulator I get expected
results, the ones which I like. If I choose ModelSim PE, outputs have
undefined value most of the time, I mean 'XXXXX' signals.
But there is another cute stuff. My testbench lasts for 1400ns. Things
which I described happen on first 1400ns. If I run it for another 1400ns
(end on 2800ns), input signals repeat just as it starts from the beginning,
but now I get 'good' results. Then if I do it again, for another 1400 ns, I
get 'XXXXX' results again.

Of course, I had to compile simulation libraries and I've done it in Xilinx
ISE. I had a lot of warnings (hundreds) only for simprim library. These are
the warnings:
-- Compiling entity x_fdd
-- Compiling architecture x_fdd_v of x_fdd
-- Compiling entity x_fddrcpe
###### C:\Xilinx92i\vhdl\src\simprims\simprim_VITAL_mti.v hd(8220):
tbpd_GSR_Q_C0 : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] C:\Xilinx92i\vhdl\src\simprims\simprim_VITAL_mti.v hd(8220):
VITAL timing generic missing port reference(s).
(1076.4 section 4.3.2.1.2)
###### C:\Xilinx92i\vhdl\src\simprims\simprim_VITAL_mti.v hd(8241):
tipd_GSR : VitalDelayType01 := (0.000 ns, 0.000 ns);
** Warning: [6] C:\Xilinx92i\vhdl\src\simprims\simprim_VITAL_mti.v hd(8241):
VITAL timing generic missing port reference.
(1076.4 section 4.3.2.1.2)
....

I don't like this warnings, of course. On the other hand, post-map
simulation worked fine on ModelSim. And after I run simulation for another
1400ns (loop it again) I got results which I like

Has anyone had similiar problems?

I can post you my code, if you like, and testbench.

Thnx for any help....


Mihovil Frater
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