Division with std_logic_vector

I need to implement a chaotic function in a design with VHDL. I use std_logic_vector signals and I need to implement 4 divisions. However, i recieve an error message saying: "Line 40. / can not have such operands in this context."

I use:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



Can you please help me?

danell

[danell]

This is the code i used:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity imp is
Port ( in1 : in STD_LOGIC_VECTOR (7 downto 0);
in2 : in STD_LOGIC_VECTOR (7 downto 0);
ies : in STD_LOGIC_VECTOR (7 downto 0));
end imp;

architecture Behavioral of imp is

begin

ies <= in1/in2;

end Behavioral;

danell

[danell]

Please comment in any way my post. Is there any way I can implement a division using std_logic_vector?

danell

[jeppe]

Check this page: Division

This gives a more interactive presentation of division: Opar1

Jeppe

jeppe

[danell]

Thank you jeppe!

I thought it was something like a spelling error, or a library I should have added. If I need to make a design, I think it is better to use the core generator from my Xilinx ISE...

danell