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simulating 8255

 
 
Shalini Keshavamurthy
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      03-02-2008
hi,
i want to simulate 8255 using vhdl.
is there any way to configure a port as an I/P or an O/P based on
certain conditions in d architecture? how do i go abt it?
 
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neha.k.ee@gmail.com
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      03-02-2008
On Mar 2, 10:56 pm, Shalini Keshavamurthy <(E-Mail Removed)>
wrote:
> hi,
> i want to simulate 8255 using vhdl.
> is there any way to configure a port as an I/P or an O/P based on
> certain conditions in d architecture? how do i go abt it?



You'd have to do it using inout ports
 
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Mark McDougall
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      03-02-2008
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:

>> i want to simulate 8255 using vhdl.


FYI been done (a few times) before...

>> is there any way to configure a port as an I/P or an O/P based on
>> certain conditions in d architecture? how do i go abt it?

> You'd have to do it using inout ports


I'd strongly suggest you don't use inout ports in your 8255 model, but
rather use input, output and output-enable ports for each 8255 IO port and
then connect them to bidir (inout) pins on the FPGA in the top level.

so:

entity 8255 is
(
...
8255_port_i : in std_logic;
8255_port_o : out std_logic;
8255_port_oe : out std_logic;
...
);

8255_port_i <= fpga_birdir_port;
fpga_bidir_port <= 8255_port_o when 8255_port_oe = '1' else 'Z';

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
 
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Shalini
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      03-03-2008
On Mar 3, 4:40*am, Mark McDougall <(E-Mail Removed)> wrote:
> (E-Mail Removed) wrote:
> >> i want to simulate 8255 using vhdl.

>
> FYI been done (a few times) before...
>
> >> is there any way to configure a port as an I/P or an O/P based on
> >> certain conditions in d architecture? how do i go abt it?

> > You'd have to do it using inout ports

>
> I'd strongly suggest you don't use inout ports in your 8255 model, but
> rather use input, output and output-enable ports for each 8255 IO port and
> then connect them to bidir (inout) pins on the FPGA in the top level.
>
> so:
>
> entity 8255 is
> (
> * ...
> * 8255_port_i * *: in std_logic;
> * 8255_port_o * *: out std_logic;
> * 8255_port_oe * : out std_logic;
> * ...
> );
>
> 8255_port_i <= fpga_birdir_port;
> fpga_bidir_port <= 8255_port_o when 8255_port_oe = '1' else 'Z';
>
> Regards,
>
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266


thanks Mark
thanks neha
 
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priyvrat5 priyvrat5 is offline
Junior Member
Join Date: Apr 2009
Posts: 1
 
      05-01-2009
Hello!

Can any body provide me 8255 Mode_1 & Mode_0 VHDL/ Verilog Code.


Regards
 
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