real to signed

How to convert real to signed. The range of real will be from -1 to 1,
-5 to 5, -10 to 10 and so on. I would like to convert this range to a
signed vector of bit width bw(generic). The data has to be scaled but
I have no idea on how to do it. I have searched on the internet and
did not find any valuable information.

FPGA

FPGA wrote:
> How to convert real to signed. The range of real will be from -1 to 1,
> -5 to 5, -10 to 10 and so on. I would like to convert this range to a
> signed vector of bit width bw(generic). The data has to be scaled but
> I have no idea on how to do it. I have searched on the internet and
> did not find any valuable information.

Google this:-

convert real signed vhdl

Click on the first link with the left button of your mouse.

HTH., Syms.

Symon

FPGA wrote:
> How to convert real to signed. The range of real will be from -1 to 1,
> -5 to 5, -10 to 10 and so on. I would like to convert this range to a
> signed vector of bit width bw(generic). The data has to be scaled but
> I have no idea on how to do it. I have searched on the internet and
> did not find any valuable information.
>

Start with modulo arithmetic.
http://deadsmall.com/3AE

Mike Treseler

On Feb 29, 2:46 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
> How to convert real to signed. The range of real will be from -1 to 1,
> -5 to 5, -10 to 10 and so on. I would like to convert this range to a
> signed vector of bit width bw(generic). The data has to be scaled but
> I have no idea on how to do it. I have searched on the internet and
> did not find any valuable information.

You will need to know magnitude width and fraction width as you will
be generating a fixed point decimal.
Magnitude width (MW) can be done by taking log2(limit) and adding 1
(to account for the sign bit).
Fraction width (FW) is then bw-MW.

Then you scale the result by 2**FW and convert it to an integer (which
then gives you your signed number).
Remember Integer(my_real) always rounds to nearest. If you dont want
to round to nearest, you have to write a function that rounds to zero,
otherwise removing the LSBs will always round down. (towards 0 for
+ve, away from 0 for -ve).

Tricky

FPGA wrote:

> How to convert real to signed. The range of real will be from -1 to 1,
> -5 to 5, -10 to 10 and so on.

I don't understand this.

> I would like to convert this range to a
> signed vector of bit width bw(generic). The data has to be scaled but
> I have no idea on how to do it.

What do you mean by scaling?

> I have searched on the internet and did not find any valuable information.

If it is only about converting from real to signed, then first convert the
real to integer, and then to signed with the to_signed function from
ieee.numeric_std.

Something like this:

LIBRARY ieee;
USE ieee.numeric_std.ALL;
...
FUNCTION real2signed
(
r: real;
return_width: positive
) RETURN signed IS
BEGIN
RETURN to_signed(integer(r), return_width);
END FUNCTION real2signed;

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.

Paul Uiterlinden

On Feb 29, 4:29 pm, Tricky <Trickyh...@gmail.com> wrote:
> On Feb 29, 2:46 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > How to convert real to signed. The range of real will be from -1 to 1,
> > -5 to 5, -10 to 10 and so on. I would like to convert this range to a
> > signed vector of bit width bw(generic). The data has to be scaled but
> > I have no idea on how to do it. I have searched on the internet and
> > did not find any valuable information.
>
> You will need to know magnitude width and fraction width as you will
> be generating a fixed point decimal.
> Magnitude width (MW) can be done by taking log2(limit) and adding 1
> (to account for the sign bit).
> Fraction width (FW) is then bw-MW.
>
> Then you scale the result by 2**FW and convert it to an integer (which
> then gives you your signed number).
> Remember Integer(my_real) always rounds to nearest. If you dont want
> to round to nearest, you have to write a function that rounds to zero,
> otherwise removing the LSBs will always round down. (towards 0 for
> +ve, away from 0 for -ve).

PS. None of this is synthesisable, as it bases all working on reals,
which you cannot synthesise in any way. Reals are only allowed to
create constants (which then have to be of a synthesizable type).

If you are trying now to synthesize your sine wave generator, you are
going about it the wrong way.

Tricky

On Feb 29, 11:50*am, Tricky <Trickyh...@gmail.com> wrote:
> On Feb 29, 4:29 pm, Tricky <Trickyh...@gmail.com> wrote:
>
>
>
>
>
> > On Feb 29, 2:46 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > > How to convert real to signed. The range of real will be from -1 to 1,
> > > -5 to 5, -10 to 10 and so on. I would like to convert this range to a
> > > signed vector of bit width bw(generic). The data has to be scaled but
> > > I have no idea on how to do it. I have searched on the internet and
> > > did not find any valuable information.
>
> > You will need to know magnitude width and fraction width as you will
> > be generating a fixed point decimal.
> > Magnitude width (MW) can be done by taking log2(limit) and adding 1
> > (to account for the sign bit).
> > Fraction width (FW) is then bw-MW.
>
> > Then you scale the result by 2**FW and convert it to an integer (which
> > then gives you your signed number).
> > Remember Integer(my_real) always rounds to nearest. If you dont want
> > to round to nearest, you have to write a function that rounds to zero,
> > otherwise removing the LSBs will always round down. (towards 0 for
> > +ve, away from 0 for -ve).
>
> PS. None of this is synthesisable, as it bases all working on reals,
> which you cannot synthesise in any way. Reals are only allowed to
> create constants (which then have to be of a synthesizable type).
>
> If you are trying now to synthesize your sine wave generator, you are
> going about it the wrong way.- Hide quoted text -
>
> - Show quoted text -

I dont want to synthesize this.

FPGA

On Feb 29, 11:32*am, Paul Uiterlinden <puit...@notaimvalley.nl> wrote:
> FPGA wrote:
> > How to convert real to signed. The range of real will be from -1 to 1,
> > -5 to 5, -10 to 10 and so on.
>
> I don't understand this.
>
> > I would like to convert this range to a
> > signed vector of bit width bw(generic). The data has to be scaled but
> > I have no idea on how to do it.
>
> What do you mean by scaling?
>
> > I have searched on the internet and did not find any valuable information.
>
> If it is only about converting from real to signed, then first convert the
> real to integer, and then to signed with the to_signed function from
> ieee.numeric_std.
real can be of type 0.0134 .. if I convert this to integer it is going
to give a 0.
>
> Something like this:
>
> * LIBRARY ieee;
> * USE ieee.numeric_std.ALL;
> * ...
> * FUNCTION real2signed
> * (
> * * r: real;
> * * return_width: positive
> * ) RETURN signed IS
> * BEGIN
> * * RETURN to_signed(integer(r), return_width);
> * END FUNCTION real2signed;
>
> --
> Paul Uiterlindenwww.aimvalley.nl
> e-mail addres: remove the not.

FPGA

On Feb 29, 11:29*am, Tricky <Trickyh...@gmail.com> wrote:
> On Feb 29, 2:46 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
>
> > How to convert real to signed. The range of real will be from -1 to 1,
> > -5 to 5, -10 to 10 and so on. I would like to convert this range to a
> > signed vector of bit width bw(generic). The data has to be scaled but
> > I have no idea on how to do it. I have searched on the internet and
> > did not find any valuable information.
>
> You will need to know magnitude width and fraction width as you will
> be generating a fixed point decimal.
> Magnitude width (MW) can be done by taking log2(limit) and adding 1
> (to account for the sign bit).

MW and FW of output real changes with change in amplitude. What is
'limit'?

> Fraction width (FW) is then bw-MW.
>
> Then you scale the result by 2**FW and convert it to an integer (which
> then gives you your signed number).
> Remember Integer(my_real) always rounds to nearest. If you dont want
> to round to nearest, you have to write a function that rounds to zero,
> otherwise removing the LSBs will always round down. (towards 0 for
> +ve, away from 0 for -ve).

FPGA

On 29 Feb., 15:46, FPGA <FPGA.unkn...@gmail.com> wrote:
> How to convert real to signed. The range of real will be from -1 to 1,
> -5 to 5, -10 to 10 and so on. I would like to convert this range to a
> signed vector of bit width bw(generic). The data has to be scaled but
> I have no idea on how to do it. I have searched on the internet and
> did not find any valuable information.

Start with understanding what a real is:
http://en.wikipedia.org/wiki/IEEE_754-1985
Than it is easy to write your conversion function.

bye Thomas

Thomas Stanka