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VHDL - Easier Way to Do Structural Design |
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I'm in the middle of working on my senior design project using ModelSim SE. I've coded all of my modules and now I'm working on the top-level design which is really all about connecting those individual modules together.
I was wondering if there is an easier to connect all these modules. Right now I just create signals to connect from one module to another. There has to be a less tedious way of doing this. Perhaps a visual interface where I can plop my modules and visually connect them? Or am I stuck with managing a ton of signals? P.S. The top-level really has no patterns or repetition, so I can't really use the "generate" statement. Thanks in advance! Hybr1dz |
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