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hi all,
I want know how to write `timescale 1 ps / 1 ps equivalent in VHDL.

sheri a écrit:
> hi all,
> I want know how to write `timescale 1 ps / 1 ps equivalent in VHDL.
>

You can't.

--
Vince

On Feb 27, 12:46*pm, Vince <debo...@free.fr> wrote:
> sheri a écrit:
>
> > hi all,
> > I want know how to write `timescale 1 ps / 1 ps equivalent in VHDL.
>
> You can't.
>
> --
> Vince

Thanks Vince.
But I want to know Is there any other way to do time_unit and
resolution settings in VHDL.

sheri a écrit:
> On Feb 27, 12:46 pm, Vince <debo...@free.fr> wrote:
>> sheri a écrit:
>>
>>> hi all,
>>> I want know how to write `timescale 1 ps / 1 ps equivalent in VHDL.
>>
>> You can't.
>>
>
> Thanks Vince.
> But I want to know Is there any other way to do time_unit and
> resolution settings in VHDL.
>

You have to look into the manual of your simulator. By example with NCSim you
can specify a timescale for VHDL components during the elaboration.

--
Vince

On Wed, 27 Feb 2008 00:19:43 -0800 (PST), sheri wrote:

>But I want to know Is there any other way to do time_unit and
>resolution settings in VHDL.

From your other post it seems you're using Modelsim.
When you launch the simulation using the vsim command,
add the option

vsim -t ps <thing_to_simulate>

(or ns, or whatever timeprecision you want).

Global timeunits make no sense in VHDL, because all time
values have explicit units. In principle VHDL can resolve
femtoseconds, but in practice simulators set a coarser
timeprecision which you can then override on the
command line.

Standard installations of Modelsim default to 1ns
precision, but (I believe) the versions that ship
with Quartus and Xilinx ISE are defaulted to 1ps.

As others have said, a similar story applies for
other simulators.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

On Feb 27, 1:51*pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Wed, 27 Feb 2008 00:19:43 -0800 (PST), sheri wrote:
> >But I want to know Is there any other way to do time_unit and
> >resolution settings in VHDL.
>
> From your other post it seems you're using Modelsim.
> When you launch the simulation using the vsim command,
> add the option
>
> * vsim -t ps <thing_to_simulate>
>
> (or ns, or whatever timeprecision you want).
>
> Global timeunits make no sense in VHDL, because all time
> values have explicit units. *In principle VHDL can resolve
> femtoseconds, but in practice simulators set a coarser
> timeprecision which you can then override on the
> command line.
>
> Standard installations of Modelsim default to 1ns
> precision, but (I believe) the versions that ship
> with Quartus and Xilinx ISE are defaulted to 1ps.
>
> As others have said, a similar story applies for
> other simulators.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Thanks Vince and Jonathan.
But similar kind of setting can be done in modelsim.ini file -
resolution option.
To reduce simulaton time I changed from ps to ns, but did not observe
any reduction.
Looks like altera - dprams need ps resolution - not sure about this.
Can you please throw some light on this as to why changing resolution
did'nt help?

sheri a écrit:
> On Feb 27, 1:51 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
>> On Wed, 27 Feb 2008 00:19:43 -0800 (PST), sheri wrote:
>>> But I want to know Is there any other way to do time_unit and
>>> resolution settings in VHDL.
>>
>> From your other post it seems you're using Modelsim.
>> When you launch the simulation using the vsim command,
>> add the option
>>
>> vsim -t ps <thing_to_simulate>
>>
>> (or ns, or whatever timeprecision you want).
>>
>> Global timeunits make no sense in VHDL, because all time
>> values have explicit units. In principle VHDL can resolve
>> femtoseconds, but in practice simulators set a coarser
>> timeprecision which you can then override on the
>> command line.
>>
>> Standard installations of Modelsim default to 1ns
>> precision, but (I believe) the versions that ship
>> with Quartus and Xilinx ISE are defaulted to 1ps.
>>
>> As others have said, a similar story applies for
>> other simulators.
>
> Thanks Vince and Jonathan.
> But similar kind of setting can be done in modelsim.ini file -
> resolution option.
> To reduce simulaton time I changed from ps to ns, but did not observe
> any reduction.
> Looks like altera - dprams need ps resolution - not sure about this.
> Can you please throw some light on this as to why changing resolution
> did'nt help?
>

What is your design? VHDL only, Verilog Only, mixed ?

--
Vince

On Feb 27, 3:20*pm, Vince <debo...@free.fr> wrote:
> sheri a écrit:
>
>
>
>
>
> > On Feb 27, 1:51 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> > wrote:
> >> On Wed, 27 Feb 2008 00:19:43 -0800 (PST), sheri wrote:
> >>> But I want to know Is there any other way to do time_unit and
> >>> resolution settings in VHDL.
>
> >> From your other post it seems you're using Modelsim.
> >> When you launch the simulation using the vsim command,
> >> add the option
>
> >> * vsim -t ps <thing_to_simulate>
>
> >> (or ns, or whatever timeprecision you want).
>
> >> Global timeunits make no sense in VHDL, because all time
> >> values have explicit units. *In principle VHDL can resolve
> >> femtoseconds, but in practice simulators set a coarser
> >> timeprecision which you can then override on the
> >> command line.
>
> >> Standard installations of Modelsim default to 1ns
> >> precision, but (I believe) the versions that ship
> >> with Quartus and Xilinx ISE are defaulted to 1ps.
>
> >> As others have said, a similar story applies for
> >> other simulators.
>
> > Thanks Vince and Jonathan.
> > But similar kind of setting can be done in modelsim.ini file -
> > resolution option.
> > To reduce simulaton time I changed from ps to ns, but did not observe
> > any reduction.
> > Looks like altera - dprams need ps resolution - not sure about this.
> > Can you please throw some light on this as to why changing resolution
> > did'nt help?
>
> What is your design? VHDL only, Verilog Only, mixed ?
>
> --
> Vince- Hide quoted text -
>
> - Show quoted text -

vhdl only.

sheri a écrit:
> On Feb 27, 3:20 pm, Vince <debo...@free.fr> wrote:
>> sheri a écrit:
>>
>>> On Feb 27, 1:51 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
>>> wrote:
>>>> On Wed, 27 Feb 2008 00:19:43 -0800 (PST), sheri wrote:
>>>>> But I want to know Is there any other way to do time_unit and
>>>>> resolution settings in VHDL.
>>
>>>> From your other post it seems you're using Modelsim.
>>>> When you launch the simulation using the vsim command,
>>>> add the option
>>
>>>> vsim -t ps <thing_to_simulate>
>>
>>>> (or ns, or whatever timeprecision you want).
>>
>>>> Global timeunits make no sense in VHDL, because all time
>>>> values have explicit units. In principle VHDL can resolve
>>>> femtoseconds, but in practice simulators set a coarser
>>>> timeprecision which you can then override on the
>>>> command line.
>>
>>>> Standard installations of Modelsim default to 1ns
>>>> precision, but (I believe) the versions that ship
>>>> with Quartus and Xilinx ISE are defaulted to 1ps.
>>
>>>> As others have said, a similar story applies for
>>>> other simulators.
>>
>>> Thanks Vince and Jonathan.
>>> But similar kind of setting can be done in modelsim.ini file -
>>> resolution option.
>>> To reduce simulaton time I changed from ps to ns, but did not observe
>>> any reduction.
>>> Looks like altera - dprams need ps resolution - not sure about this.
>>> Can you please throw some light on this as to why changing resolution
>>> did'nt help?
>>
>> What is your design? VHDL only, Verilog Only, mixed ?
>>
>
> vhdl only.
>

Ok, so you have to change the design (add change models, gated clock, reduce
clock divisor...).

--
Vince

On Wed, 27 Feb 2008 02:08:52 -0800 (PST), sheri wrote:

>Thanks Vince and Jonathan.
>But similar kind of setting can be done in modelsim.ini file -
>resolution option.

Sure.

>To reduce simulaton time I changed from ps to ns, but did not observe
>any reduction.

Why do you expect that change to improve simulation speed?
VHDL simulators are event driven. The simulator does NOT
do extra work on each time-resolution "time tick".
Consequently, the only speed improvement you might see
by degrading the resolution to ns is that the rounding
of time values to the nearest ns might possibly cause some
events to appear to be simultaneous; this *might* have a
tiny effect on simulation speed but it's unlikely to be
noticeable. And, as you point out below, it may break
some models.

>Looks like altera - dprams need ps resolution - not sure about this.

Yes, I believe that's true. This is why the Altera and Xilinx
versions of the simulator default to picosecond resolution.

>Can you please throw some light on this as to why changing resolution
>did'nt help?

I suspect you are trying to simulate a large design with a free
version of the simulator. It is hobbled: as your design gets
larger (more lines of executable code) the simulator's speed
degrades, first by about a factor of 5, and then by a much
larger factor. The idea is that the simulator is fully functional
so that you can experiment with it and see what it can do, but
it is useless for simulating large-scale projects - so you are
encouraged to spend real money on the full-performance real
version.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.