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VHDL - an error multiple sources

 
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Old 02-27-2008, 06:51 AM   #1
Question an error multiple sources


Hi, All,
I encounter an error when comply with MAX+PLUS II

-- part of the code as follow: --

architecture bhv of calculator is
signal a,b,c,d,oper1,oper2 : std_logic_vector(3 downto 0);
signal x,y,tmp : std_logic_vector(7 downto 0);
signal EQ : std_logic_vector(1 downto 0);

--- another Process ---

Calculaterocess(EQ,oper1,oper2)
variable tmp,tmp_x,tmp_y,tmp_ans : std_logic_vector(7 downto 0);
begin
tmp_x<=x;
tmp_y<=y;
if EQ="01" then

if oper1="1010" then --- +
tmp:=tmp_x+tmp_y;
elsif oper1="1011" then --- -
tmp:=tmp_x-tmp_y;
elsif oper1="1100" then --- x
tmp:=tmp_x*tmp_y;
elsif oper1="1110" then --- /
for i in 0 to 10 loop
if tmp_x>=tmp_y then
tmp_ans:=tmp_ans+"00000001";
tmp_x:=tmp_x-tmp_y;
tmp:=tmp_ans;
end if;
end loop;
end if;

elsif EQ=10" then
if oper1="1010" then
tmp:=tmp_x+tmp_y;
elsif oper2="1010" then
tmp:=tmp_x+tmp_y;
elsif oper2="1011" then
tmp:=tmp_x-tmp_y;
end if;

elsif EQ="11" then
if oper2="1010" then
tmp:=tmp_x+tmp_y;
elsif oper2="1011" then
if tmp_x>=tmp_y then
tmp:=tmp_x-tmp_y;
else
null;
end if;
end if;

else
tmp:=(others=>'0');
tmp_x:=(others=>'0');
tmp_y:=(others=>'0');
tmp_ans:=(others=>'0');
end if;

Ans<=tmp;
end process;

I don't find any multiple source for it. I can't understand. Can anyone
help me explain it? please help me. This's my last chance. Thank you

Regards
ViaTy


ViaTy
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