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VHDL - please help me check my coding |
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#1 |
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ontime range is 0,1,2.. to 199.
count1a range is 1, 3, 5 .. to 199 (odd numbers). count1b range is 0, 2, 4 .. to 198 (even numbers). counter1 range is 0,1,2... to 99. i have two processes both with same input signal clk. 1st process will count the rising edge while the 2nd process will count the falling edge. time between rising edge and falling edge is 5ns. when i run this code in simulation, i am able to achieve 5ns increment from the output when i increment the ontime by 1. but when i do the experiment on the circuit, i can only achieve 10ns increment. for example, the results i got for ontime= 100, 101, 102, 103, 104, 105 are 40ns, 50ns, 50ns, 60ns, 60ns, 70ns respectively. may i know where did i went wrong in my coding or is there any illegal statement? please advise.. thank you. process (clk, reset) --first process to take care of rising edge if reset = '0' then count1a := 1; elsif (rising_edge(clk)) then if (counter1 = 0) then count1a := 1; --count1a will be odd number, 1, 3, 5 .. 199. else count1a := count1a + 1; end if; end if; end process; process (clk, reset) --2nd process to take care of falling edge if reset = '0' then count1b := 0; --count1b will be even numbers, 0, 2, 4 .. 198. counter1 := 0; elsif (falling_edge(clk)) then if (counter1 = 0) then count1b := 0; end if; if (counter1 >= 99) then counter1 := 0; else counter1 := counter1 + 1; count1b := count1b + 2; end if; ontime := XX; ontime1 := XX + 1; if (ontime1/2 = ontime/2) then --even ontime number if(count1b < ontime) then out1 <= '1'; -- out1 is my output signal else out1 <= '0'; end if; else -- odd ontime number if(count1a < ontime) then out1 <= '1'; else out1 <= '0'; end if; end if; end process; raullim7@hotmail.com |
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#2 |
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Posts: n/a
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process (clk, reset) --first process to take care of rising edge
if reset = '0' then count1a := 1; elsif (rising_edge(clk)) then if (counter1 = 0) then count1a := 1; --count1a will be odd number, 1, 3, 5 .. 199. else count1a := count1a + 2; end if; end if; end process; **made a mistake here, should be count1a := count1a + 2, not + 1. raullim7@hotmail.com |
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