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Hi,

We have a large mixed language (ASIC) design, for which we will be
using scan insertion and ATPG to generate manufacturing test.

However, the is one part (seperate power domain) of the design which
will not follow the standard design flow. It is asynchronous logic,
required very low (leakage and active) power etc. We intend to write
functional vectors for this part of the design. The section will be
"designed" as hand crafted verilog netlist.

I have a couple of questions
- Does anyone know of a free (cheap) ATPG generation tool that will
work for non scan designs?
(I remember in the past that Mento Graphics had two tools. Fast Scan
and another Flex Test, one for scan, and one for non scan)
- Does anyone know of a free (cheap) fault simulator that will accept
verilog netlist input.
(this would be useful if we need to generate the vectors by hand).
To my limited knowledge, fault simulation ought to be reasonably easy
to write as an addon to a standard verilog simulator (if you don't
need any clever acceleration).

Thanks,

Steven

wrote:
> Hi,
>
> We have a large mixed language (ASIC) design, for which we will be
> using scan insertion and ATPG to generate manufacturing test.
>
> However, the is one part (seperate power domain) of the design which
> will not follow the standard design flow. It is asynchronous logic,
> required very low (leakage and active) power etc. We intend to write
> functional vectors for this part of the design. The section will be
> "designed" as hand crafted verilog netlist.
>
> I have a couple of questions
> - Does anyone know of a free (cheap) ATPG generation tool that will
> work for non scan designs?
> (I remember in the past that Mento Graphics had two tools. Fast Scan
> and another Flex Test, one for scan, and one for non scan)

Syntest have turbofault. Not sure how much it costs.

> - Does anyone know of a free (cheap) fault simulator that will accept
> verilog netlist input.
> (this would be useful if we need to generate the vectors by hand).

ATPG tools can use sequemtial ATPG to test a limited amount of logic in
between flip-flops. It is not quick.

Ask yourself if you can get enough stuck at coverage tu gurantee 50dppm?
Can you convince your customer that you can do it. Can you do Iddq, path
delay faults, transition faults or bridging faults?
> To my limited knowledge, fault simulation ought to be reasonably easy
> to write as an addon to a standard verilog simulator (if you don't
> need any clever acceleration).
>
> Thanks,
>
> Steven
>
>

On Feb 21, 3:10*pm, moo...@yahoo.co.uk wrote:
>
> - Does anyone know of a free (cheap) fault simulator that will accept
> verilog netlist input.
> To my limited knowledge, fault simulation ought to be reasonably easy
> to write as an addon to a standard verilog simulator (if you don't
> need any clever acceleration).

The problem is that fault simulation takes a very long time if you
don't do any clever acceleration.

The only thing that would be easy to write as an add-on to a standard
simulator would be sequential fault simulation. If you have N
possible faults in your circuit, you do N simulations, each a
simulation of the circuit with one of the N faults injected. This
takes about N times as long as doing one simulation. For a circuit of
any size, this is very expensive. On the plus side, this could be
written as an addon to any standard Verilog simulator using PLI. You
might even be able to find one that someone has already written
(assuming simple stuck-at faults are good enough for your purposes).

On 21 Feb., 21:10, moo...@yahoo.co.uk wrote:
> - Does anyone know of a free (cheap) fault simulator that will accept
> verilog netlist input.
> (this would be useful if we need to generate the vectors by hand).
> To my limited knowledge, fault simulation ought to be reasonably easy
> to write as an addon to a standard verilog simulator (if you don't
> need any clever acceleration).

"Fault simulation" is included for free in most simulators, but you
need stimuli that cover each fault. The stimuli generation is not for
free. And collecting the reached coverage data for given stimuli is
also not that easy part, as you need to identify not only if a fault
on the gate input affects the gate output, but also if this fault
would be observable. This task seems to me especially difficult in
asynchronous logic. I wonder if there is already a tool available that
covers ATPG for asynchronous logic.

bye Thomas