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neilmac neilmac is offline
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Join Date: Jan 2008
Posts: 5
 
      02-15-2008
If I have a signal called jim, which is a vector of, say, 7 downto 0 and in a clk'd process I make these assignments to this signal for a given a case condition :

when condition_true

-- set all bits to zero
jim <= (others => '0');
-- set bit 4 active to '1'
jim(4) <= '1';


...will jim have all bits set to '0' apart from bit 4. Jim is a signal.

I think it will and this works but in terms of synthese do you have to assign to others first and then assign the bits you want to change or does it not matter?
 
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gzidude gzidude is offline
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Join Date: Feb 2008
Posts: 19
 
      02-17-2008
Your code is making two assignments to jim at the same time. Your compiler should puke all over you. It assigns jim(4) to '0' and jim(4) to '1' concurrently since they're being clocked together.

This should work:

when condition_true

-- set all bits at same time
jim <= (4 => '1', others => '0')
 

Last edited by gzidude; 02-17-2008 at 06:27 AM..
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