I usually use a maximal LFSR to obtain psuedo random numbers.

The following link will give you some good information.

http://www.xilinx.com/ipcenter/catal.../docs/lfsr.pdf
I like Appendix B wich lists the tap points up to 168bits for a maximal

length LFSR.

The following would generate psudeo random 64 bit numbers starting with seed

value 1.

entity generator is

port (

clk:in bit;

a

ut bit_vector(63 downto 0));

end;

achitecture processflow of generator is

begin

CLKED

rocess

variable temp:bit_vector(63 downto 0) :=

X"0000_0000_0000_0001";

begin

temp := temp(63 downto 0 ) & (temp(63) xor temp(62) );

a <= temp;

wait until (clk = '0');

end process

end

"glen herrmannsfeldt" <(E-Mail Removed)> wrote in message

news:(E-Mail Removed). ..

> FPGA wrote:

>

>> I would like to know if VHDL already has functions defined to generate

>> Random Numbers.

>

>> If not, which would be the best algorithm for generating random

>> numbers for implementation on an FPGA.

>

> LFSR are pretty popular for random numbers, and very easy to

> implement in an FPGA.

>

> -- glen

>