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Hello members,

I would like to know if VHDL already has functions defined to generate
Random Numbers.

If not, which would be the best algorithm for generating random
numbers for implementation on an FPGA.

Thank you

Good luck with the random numbers, but if you want pseudo-random:
http://en.wikipedia.org/wiki/LFSR.

Xilinx also has an excellent document on LFSRs with polynomials up to
about 1000 bits or so.

> I would like to know if VHDL already has functions defined to generate
> Random Numbers.

google is your friend

http://www.velocityreviews.com/forum...generator.html


> If not, which would be the best algorithm for generating random
> numbers for implementation on an FPGA.

The answer to this question will depend on the FPGA architecture that
you're using, as well as your needs for cryptographic security. This
is because, when it comes to pseudo-random number generation, "best"
can be subjective. e.g., "best" speed? "best" area? "best" power
consumption? "best" random numbers (cryptographically secure)?

This is a well-studied area; I recommend that you do some reading to
see what suits you ...

http://en.wikipedia.org/wiki/Random_number_generator


Kris

On 24 Jan., 18:54, FPGA <FPGA.unkn...@gmail.com> wrote:
> Hello members,
>
> I would like to know if VHDL already has functions defined to generate
> Random Numbers.
>
> If not, which would be the best algorithm for generating random
> numbers for implementation on an FPGA.
>
> Thank you

Hello FPGA,

Maybe it's off-topic for you, because you want to implement in FPGA
rather than simulating your design,
but have you seen this package :
http://www.janick.bergeron.com/wtb/packages/random1.vhd ?


Ed

FPGA wrote:

> I would like to know if VHDL already has functions defined to generate
> Random Numbers.

> If not, which would be the best algorithm for generating random
> numbers for implementation on an FPGA.

LFSR are pretty popular for random numbers, and very easy to
implement in an FPGA.

-- glen

On Jan 25, 1:01*am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> FPGA wrote:
> > I would like to know if VHDL already has functions defined to generate
> > Random Numbers.
> > If not, which would be the best algorithm for generating random
> > numbers for implementation on an FPGA.
>
> LFSR are pretty popular for random numbers, and very easy to
> implement in an FPGA.
>
> -- glen

I just found out that I need random number generator just for
simulation. I do not need to synthesize it. Some feedback on this
would be helpful. I am having a look at some of the links posted here.

Thanks

I usually use a maximal LFSR to obtain psuedo random numbers.

The following link will give you some good information.
http://www.xilinx.com/ipcenter/catal.../docs/lfsr.pdf

I like Appendix B wich lists the tap points up to 168bits for a maximal
length LFSR.

The following would generate psudeo random 64 bit numbers starting with seed
value 1.

entity generator is
port (
clk:in bit;
aut bit_vector(63 downto 0));
end;


achitecture processflow of generator is
begin
CLKEDrocess
variable temp:bit_vector(63 downto 0) :=
X"0000_0000_0000_0001";
begin
temp := temp(63 downto 0 ) & (temp(63) xor temp(62) );
a <= temp;
wait until (clk = '0');
end process
end

"glen herrmannsfeldt" <> wrote in message
news:. ..
> FPGA wrote:
>
>> I would like to know if VHDL already has functions defined to generate
>> Random Numbers.
>
>> If not, which would be the best algorithm for generating random
>> numbers for implementation on an FPGA.
>
> LFSR are pretty popular for random numbers, and very easy to
> implement in an FPGA.
>
> -- glen
>

Ann wrote:
(snip)

> I just found out that I need random number generator just for
> simulation. I do not need to synthesize it. Some feedback on this
> would be helpful. I am having a look at some of the links posted here.

LFSR are fairly popular now for software implementations, though
linear congruential generators are also still popular.

Linear congruential is probably easy for simulation, not quite
as easy as LFSR for synthesis.

The favorite reference is Knuth, "The Art of Computer Programming",
volume 2. Worth having for anyone working with computers.

-- glen

some typos:

> achitecture processflow of generator is

architecture

> temp := temp(63 downto 0 ) & (temp(63) xor temp(62) );
1
> end process
;
> end
;

Mike Treseler a écrit :
> some typos:
>
>> achitecture processflow of generator is
>
> architecture
>
>> temp := temp(63 downto 0 ) & (temp(63) xor temp(62) );
> 1
>> end process
> ;
>> end
> ;

temp := temp(62 downto 0) & (temp(63) xor temp(62) );

(shift register)