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Impossible Equation

 
 
Ndf
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      01-24-2008
Hello,

I have a design that should output TRUE or FALSE as the result of a very
large equation made with 256 inputs combined by 8! There are about 7 000
000 lines of code like below!!

Anybody know of a VHDL compiler capable to optimize such a huge equation?

Thanks!


Pout <=
(Pinp(13) and Pinp(4) and Pinp(63) and Pinp(4 and Pinp(16) and Pinp(5) and
Pinp(112) and Pinp(45)) or
(Pinp(13) and Pinp(4) and Pinp(63) and Pinp(4 and Pinp(16) and Pinp(10)
and Pinp(224) and Pinp(3) or
(Pinp(13) and Pinp(4) and Pinp(63) and Pinp(4 and Pinp(16) and Pinp(19)
and Pinp(224) and Pinp(3) or
(Pinp(13) and Pinp(4) and Pinp(63) and Pinp(4 and Pinp(16) and Pinp(25)
and Pinp(77) and Pinp(37)) or
(Pinp(13) and Pinp(4) and Pinp(63) and Pinp(4 and Pinp(16) and Pinp(25)
and Pinp(89) and Pinp(44)) or
(Pinp(13) and Pinp(4) and Pinp(63) and Pinp(4 and Pinp(16) and Pinp(30)
and Pinp(224) and Pinp(3) or
(Pinp(13) and Pinp(4) and Pinp(63) and Pinp(4 and Pinp(16) and Pinp(32)
and Pinp(229) and Pinp(45)) or
(Pinp(13) and Pinp(4) and Pinp(63) and Pinp(4 and Pinp(16) and Pinp(39)
and Pinp(237) and Pinp(44)) or
(Pinp(13) and Pinp(4) and Pinp(63) and Pinp(4 and Pinp(16) and Pinp(42)
and Pinp(224) and Pinp(3) or
(Pinp(13) and Pinp(4) and Pinp(63) and Pinp(4 and Pinp(16) and Pinp(50)
and Pinp(112) and Pinp(45)) or
(Pinp(13) and Pinp(21) and Pinp(251) and Pinp(252) and Pinp(19 and
Pinp(213) and Pinp(211) and Pinp(37)) or
(Pinp(13) and Pinp(21) and Pinp(251) and Pinp(252) and Pinp(19 and
Pinp(213) and Pinp(219) and Pinp(3) or
(Pinp(13) and Pinp(21) and Pinp(251) and Pinp(252) and Pinp(19 and
Pinp(216) and Pinp(211) and Pinp(37)) or
(Pinp(13) and Pinp(21) and Pinp(251) and Pinp(252) and Pinp(19 and
Pinp(216) and Pinp(219) and Pinp(3) or
(Pinp(13) and Pinp(21) and Pinp(251) and Pinp(252) and Pinp(19 and
Pinp(232) and Pinp(237) and Pinp(44)) or
(Pinp(13) and Pinp(21) and Pinp(251) and Pinp(252) and Pinp(19 and
Pinp(23 and Pinp(237) and Pinp(44)) or
(Pinp(13) and Pinp(21) and Pinp(251) and Pinp(252) and Pinp(19 and
Pinp(239) and Pinp(237) and Pinp(44)) or
(Pinp(13) and Pinp(21) and Pinp(251) and Pinp(252) and Pinp(19 and
Pinp(243) and Pinp(224) and Pinp(3) or
(Pinp(13) and Pinp(21) and Pinp(251) and Pinp(252) and Pinp(19 and
Pinp(249) and Pinp(224) and Pinp(3) or
(Pinp(13) and Pinp(24) and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(5)
and Pinp(112) and Pinp(45)) or
(Pinp(13) and Pinp(24) and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(10)
and Pinp(224) and Pinp(3) or
(Pinp(13) and Pinp(24) and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(19)
and Pinp(224) and Pinp(3) or
(Pinp(13) and Pinp(24) and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(25)
and Pinp(77) and Pinp(37)) or
(Pinp(13) and Pinp(24) and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(25)
and Pinp(89) and Pinp(44)) or
(Pinp(13) and Pinp(24) and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(30)
and Pinp(224) and Pinp(3) or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(244) and Pinp(179) and Pinp(6)) or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(247) and Pinp(11 and Pinp(9)) or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(247) and Pinp(142) and Pinp(6)) or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(247) and Pinp(210) and Pinp(9)) or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(247) and Pinp(224) and Pinp() or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(24 and Pinp(11 and Pinp(9)) or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(24 and Pinp(142) and Pinp(6)) or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(250) and Pinp(12 and Pinp(5)) or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(250) and Pinp(233) and Pinp(9)) or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(251) and Pinp(11 and Pinp(9)) or
(Pinp(24) and Pinp(50) and Pinp(129) and Pinp(254) and Pinp(120) and
Pinp(251) and Pinp(142) and Pinp(6)) or
(Pinp(24) and Pinp(5 and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(5)
and Pinp(121) and Pinp(6)) or
(Pinp(24) and Pinp(5 and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(10)
and Pinp(210) and Pinp(9)) or
(Pinp(24) and Pinp(5 and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(10)
and Pinp(224) and Pinp() or
(Pinp(24) and Pinp(5 and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(1
and Pinp(179) and Pinp(6)) or
(Pinp(24) and Pinp(5 and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(19)
and Pinp(210) and Pinp(9)) or
(Pinp(24) and Pinp(5 and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(19)
and Pinp(224) and Pinp() or
(Pinp(24) and Pinp(5 and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(30)
and Pinp(210) and Pinp(9)) or
(Pinp(24) and Pinp(5 and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(30)
and Pinp(224) and Pinp() or
(Pinp(24) and Pinp(5 and Pinp(125) and Pinp(49) and Pinp(16) and Pinp(39)
and Pinp(102) and Pinp(5)) or
……………………………………………
……………………………………………


 
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Jonathan Bromley
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      01-24-2008
On Thu, 24 Jan 2008 16:31:33 +0100,
Ndf <(E-Mail Removed)> wrote:

>I have a design that should output TRUE or FALSE as the result of a very
>large equation made with 256 inputs combined by 8! There are about 7 000
>000 lines of code like below!!
>
>Anybody know of a VHDL compiler capable to optimize such a huge equation?


No, I would expect many tools to choke on it - but what are
you REALLY trying to do? What's the condition you're trying
to check? There may be an alternative way to compute it.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
http://www.velocityreviews.com/forums/(E-Mail Removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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Ndf
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      01-24-2008
This if for fun: I try to resolve a puzzle :0)

In the same time I start some research about logic optimization and I hope
to reduce this equation enough to fit inside a FPGA.







"Jonathan Bromley" <(E-Mail Removed)> a ιcrit dans le message
de news:(E-Mail Removed)...
> On Thu, 24 Jan 2008 16:31:33 +0100,
> Ndf <(E-Mail Removed)> wrote:
>
> >I have a design that should output TRUE or FALSE as the result of a very
> >large equation made with 256 inputs combined by 8! There are about 7 000
> >000 lines of code like below!!
> >
> >Anybody know of a VHDL compiler capable to optimize such a huge equation?

>
> No, I would expect many tools to choke on it - but what are
> you REALLY trying to do? What's the condition you're trying
> to check? There may be an alternative way to compute it.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> (E-Mail Removed)
> http://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.



 
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KJ
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      01-24-2008
On Jan 24, 10:31*am, "Ndf" <(E-Mail Removed)> wrote:
> Hello,
>
> I have a design that should output TRUE or FALSE as the result of a very
> large equation made with 256 inputs combined by 8! *There are about 7 000
> 000 lines of code like below!!
>
> Anybody know of a VHDL compiler capable to optimize such a huge equation?
>


Have you simply tried your 7 million lines of code either with
Modelsim (for a simulation result) or Quartus, XST, etc. (for an FPGA
synthesis result)? Who knows, it might work right out of the shoot.

Kevin Jennings
 
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Jonathan Bromley
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      01-24-2008
On Thu, 24 Jan 2008 17:32:30 +0100, "Ndf" <(E-Mail Removed)>
wrote:

>This if for fun: I try to resolve a puzzle :0)


Eight queens?

Like I said.... there may be other ways.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(E-Mail Removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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Ndf
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      01-24-2008
Thanks Kevin!

For the moment I tried with Lattice ispLEVER and ModelSim! The output error
is something like "Memory allocation failure"!




 
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Pascal Peyremorte
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Posts: n/a
 
      01-24-2008
Ndf a ιcrit :
> Hello,
>
> I have a design that should output TRUE or FALSE as the result of a very
> large equation made with 256 inputs combined by 8! There are about 7 000
> 000 lines of code like below!!


Hi,

As I'm sure you have not typed in the 7M lines, you may have generated them from
an algorithm.
Describe the same algorithm in VHDL and you will have your solution !
 
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Paul Floyd
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      01-24-2008
On Thu, 24 Jan 2008 18:00:44 +0100, Ndf <(E-Mail Removed)> wrote:
> Thanks Kevin!
>
> For the moment I tried with Lattice ispLEVER and ModelSim! The output error
> is something like "Memory allocation failure"!


Hi

Can you try on a 64bit platform (Solaris x86/SPARC, Linux Itanium/x64)?

A bientot
Paul
(Not speaking for Mentor Graphics)
--
Paul Floyd http://paulf.free.fr
 
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KJ
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      01-24-2008
On Jan 24, 12:00*pm, "Ndf" <(E-Mail Removed)> wrote:
> Thanks Kevin!
>
> For the moment I tried with Lattice ispLEVER and ModelSim! The output error
> is something like "Memory allocation failure"!


As an experiment, try chopping off half of the file and try again.
Keep doing that and you'll be able to zero in on what the rough file
size/line size/whatever size constraint is being hammered. The
purpose of the experiment is to get a handle on what the constraint is
so you can avoid it, not to solve the entire problem.

Once you've done that go back to your original 7M file and break it
down into the size file that the tools are happy with. Put a top
level wrapper around it all to 'or' it all together and then try to
synthesize/simulate the entire design and see if everything still
hangs togeter.

The better solution as others have suggested is to not work directly
with the 7M file that you've got since obviously some algorithm
generated that file in the first place but I'm assuming you don't have
access to that and you have to work with the 7M file whether want to
or not.

Good luck

Kevin Jennings
 
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backhus
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      01-25-2008
Ndf schrieb:
> This if for fun: I try to resolve a puzzle :0)
>
> In the same time I start some research about logic optimization and I hope
> to reduce this equation enough to fit inside a FPGA.
>

Hi Ndf,

we want to have some fun too...what is the puzzle?

regards
Eilert















 
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