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numeric_bit/numeric_std? std_ulogic/std_logic?

 
 
Amal
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      01-10-2008
I have a few questions that I might have my ownn answers, but it
always comes back and bugs me.

1. Would you comment on the usage of these packages? Where would one
use numeric_bit instead of numeric_std?

My understanding is that numeric_bit defines unsigned and signed
numbers as array of bits that has two values ('0', '1'). And no
resolution function. So does this makes simulations faster? And why
not use numeric_bit if there is no tri-state bus ('Z') or no need for
signal strengths ('L', 'H') or unknowns ('U', 'X', 'W')?

Again, this question might have come up before.

2. On the use of std_logic(_vector) and std_ulogic(_vector). If there
are no multiple tri-statable drivers and no wired and/or, ... bus,
should one use std_ulogic(_vector)? What are the advantages/
disadvantages?

3. Using numeric_bit or numeric_std, how does one convert a single bit
to an integer? to_integer(unsigned(b)) does not work!

Cheers,
-- Amal
 
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Jim Lewis
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      01-10-2008
Amal
> 1. Would you comment on the usage of these packages? Where would one
> use numeric_bit instead of numeric_std?

Bit does not have X. I consider this essential for seeing things
like unintialized registers. So I only use std_logic family and
as a result use only numeric_std.


> 2. On the use of std_logic(_vector) and std_ulogic(_vector). If there
> are no multiple tri-statable drivers and no wired and/or, ... bus,
> should one use std_ulogic(_vector)? What are the advantages/
> disadvantages?

The disadvantage of the current implementation of std_logic_vector and
std_ulogic_vector is that they are not subtypes of the same type and
will not convert implicitly like std_logic and std_ulogic do.

Historically a one of the synthesis vendors had ports on their
macrocells the were std_logic_vector and they did not play nice
with std_ulogic_vector, so life was easier if one used std_logic_vector.

In the next language revision, resolution functions are able to be
applied to array types and the definition of std_logic_vector has
been changed so that it is a subtype of std_ulogic_vector, and hence,
the two will convert implicitly.

WRT simulation performance, this is something you have to measure
as logic may say one thing, optimization may change your logic.

> 3. Using numeric_bit or numeric_std, how does one convert a single bit
> to an integer? to_integer(unsigned(b)) does not work!


An easy one to understand is:
to_integer(unsigned'("0" & b))

I suspect the following also work:
to_integer(unsigned'("" & b)) -- makes b a 1 bit array

to_integer(unsigned'(0 => b)) -- a 1 bit aggregate with named association


Cheers,
Jim
 
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KJ
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      01-11-2008
On Jan 10, 10:47*am, Amal <(E-Mail Removed)> wrote:
<snip>

Rather than repeat what Jim says, I'll simply say that I agree with
it.

> 2. On the use of std_logic(_vector) and std_ulogic(_vector). *If there
> are no multiple tri-statable drivers and no wired and/or, ... bus,
> should one use std_ulogic(_vector)? *What are the advantages/
> disadvantages?


What Jim didn't comment on is the benefit of std_ulogic(vector) and
that is that you won't waste any time simulating to find that you have
inadvertantly connected multiple drivers to a signal that you intend
to only have one source. By using std_ulogic(vector), you're telling
the compiler that there is only one driver so it will immediately flag
when you connect more. Granted this situation generally only comes up
in the earlier stages of a design when you're still trying to put
things together but you can still end up wasting chunks of time
debugging down to this problem that the compiler could have told you
about right up front.

As to the conversions to/from that are required for the vector forms,
they cause a bit more typing but not that much. The issue comes up
when interfacing to a component that has std_logic_vector that for
whatever reason you can't simply change. But the conversion to
std_logic_vector can be put right in to the port map for input signals
to the component; for outputs you simply define a new std_logic_vector
signal that only gets used to connect with the output of that
component and then is input to the conversion function and nowhere
else needs to be used...all and all it's not that bad.

Kevin Jennings
 
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