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How to write a VHDL code for 1Hz signal?

 
 
Vagant
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      01-08-2008
Hello,

I am a newbie to VHDL programming and want to test my FPGA board with
a code which lights a LED every second. To do this I need a VHDL code
for 1 Hz signal generator. Unfortunately, I cannot find such in Web.
Also I am not experienced in VHDL programming and not sure how to
write such a code. If you have any similar code could you put it in
this thread, please or give me some idea how to write this. I also
wonder - is it necessary to use a clock for such signal generator?
 
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Ralf Hildebrandt
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      01-08-2008
Vagant schrieb:

> I am a newbie to VHDL programming and want to test my FPGA board with
> a code which lights a LED every second. To do this I need a VHDL code
> for 1 Hz signal generator. Unfortunately, I cannot find such in Web.


Take your clock (which is running at X MHz) and divide it by X.


process(reset_n,clk)
variable cnt : integer;
begin
if (reset_n='0') then
clk_out<='0';
cnt:=0;
elsif rising_edge(clk) then
if (cnt=divider_half-1) then
clk_out<=NOT(clk_out);
cnt:=0;
else
cnt:=cnt+1;
end if;
end if;
end process;

Note that divider_half is X/2.

The code is not tested - just written in the mail program.

Ralf
 
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Vagant
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      01-08-2008
On Jan 8, 10:22*pm, Ralf Hildebrandt <(E-Mail Removed)> wrote:
> Vagant schrieb:
>
> > I am a newbie to VHDL programming and want to test my FPGA board with
> > a code which lights a LED every second. To do this I need a VHDL code
> > for 1 Hz signal generator. Unfortunately, I cannot find such in Web.

>
> Take your clock (which is running at X MHz) and divide it by X.
>
> process(reset_n,clk)
> variable * cnt * : integer;
> begin
> if (reset_n='0') then
> * * * * clk_out<='0';
> * * * * cnt:=0;
> elsif rising_edge(clk) then
> * * * * if (cnt=divider_half-1) then
> * * * * * * * * clk_out<=NOT(clk_out);
> * * * * * * * * cnt:=0;
> * * * * else
> * * * * * * * * cnt:=cnt+1;
> * * * * end if;
> end if;
> end process;
>
> Note that divider_half is X/2.
>
> The code is not tested - just written in the mail program.
>
> Ralf


Thank you. I just wonder where I could get a complete listing (which
includes 'entity' part)?
 
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Mike Treseler
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      01-08-2008
Vagant wrote:

> Thank you. I just wonder where I could get a complete listing (which
> includes 'entity' part)?


Do you have a text editor?
Didn't the board come with some examples?

Here's a related example including an entity:
http://home.comcast.net/~mike_treseler/count_enable.vhd

-- Mike Treseler
 
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Vagant
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      01-08-2008
On Jan 8, 10:22*pm, Ralf Hildebrandt <(E-Mail Removed)> wrote:
>
> Take your clock (which is running at X MHz) and divide it by X.
>

I guess it should be divided by X*10^6 to get 1 Hz, isn't it?
 
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Vagant
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Posts: n/a
 
      01-09-2008
On Jan 8, 11:12*pm, Mike Treseler <(E-Mail Removed)> wrote:
> Vagant wrote:
> > Thank you. I just wonder where I could get a complete listing (which
> > includes 'entity' part)?

>
> Do you have a text editor?
> Didn't the board come with some examples?
>
> Here's a related example including an entity:http://home.comcast.net/~mike_treseler/count_enable.vhd
>
> * * * * -- Mike Treseler


No, it's not what I am asking about.
 
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Vagant
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Posts: n/a
 
      01-09-2008
On Jan 8, 10:22*pm, Ralf Hildebrandt <(E-Mail Removed)> wrote:
> Vagant schrieb:
>
> > I am a newbie to VHDL programming and want to test my FPGA board with
> > a code which lights a LED every second. To do this I need a VHDL code
> > for 1 Hz signal generator. Unfortunately, I cannot find such in Web.

>
> Take your clock (which is running at X MHz) and divide it by X.
>
> process(reset_n,clk)
> variable * cnt * : integer;
> begin
> if (reset_n='0') then
> * * * * clk_out<='0';
> * * * * cnt:=0;
> elsif rising_edge(clk) then
> * * * * if (cnt=divider_half-1) then
> * * * * * * * * clk_out<=NOT(clk_out);
> * * * * * * * * cnt:=0;
> * * * * else
> * * * * * * * * cnt:=cnt+1;
> * * * * end if;
> end if;
> end process;
>
> Note that divider_half is X/2.
>
> The code is not tested - just written in the mail program.
>
> Ralf


However the syntax check gives an error message:

Parameter clk_out of mode out can not be associated with a formal
parameter of mode in.

for the line:
clk_out<=NOT(clk_out);
 
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neeraj2608@gmail.com
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Posts: n/a
 
      01-09-2008
On Jan 9, 2:57 am, Vagant <(E-Mail Removed)> wrote:
> On Jan 8, 10:22 pm, Ralf Hildebrandt <(E-Mail Removed)> wrote:
>
> > Take your clock (which is running at X MHz) and divide it by X.

>
> I guess it should be divided by X*10^6 to get 1 Hz, isn't it?


Not really. You're already using your clk to increment cnt. You just
need to divide it by X.

For instance, if you had a clock running at 50 MHz, cnt would
increment 50,000 times a second. Divide it by 50 and you're left with
a cnt that increments a thousand times a second - a 1 MHz clock.
 
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Vagant
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      01-09-2008
On Jan 9, 8:23*am, (E-Mail Removed) wrote:
> On Jan 9, 2:57 am, Vagant <(E-Mail Removed)> wrote:
>
> > On Jan 8, 10:22 pm, Ralf Hildebrandt <(E-Mail Removed)> wrote:

>
> > > Take your clock (which is running at X MHz) and divide it by X.

>
> > I guess it should be divided by X*10^6 to get 1 Hz, isn't it?

>
> Not really. You're already using your clk to increment cnt. You just
> need to divide it by X.
>
> For instance, if you had a clock running at 50 MHz, cnt would
> increment 50,000 times a second. Divide it by 50 and you're left with
> a cnt that increments a thousand times a second - a 1 MHz clock.


Well, but I need 1 Hz clock not 1 MHz.
 
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neeraj2608@gmail.com
Guest
Posts: n/a
 
      01-09-2008
On Jan 9, 11:23*am, Vagant <(E-Mail Removed)> wrote:
> On Jan 8, 10:22*pm, Ralf Hildebrandt <(E-Mail Removed)> wrote:
>
>
>
>
>
> > Vagant schrieb:

>
> > > I am a newbie to VHDL programming and want to test my FPGA board with
> > > a code which lights a LED every second. To do this I need a VHDL code
> > > for 1 Hz signal generator. Unfortunately, I cannot find such in Web.

>
> > Take your clock (which is running at X MHz) and divide it by X.

>
> > process(reset_n,clk)
> > variable * cnt * : integer;
> > begin
> > if (reset_n='0') then
> > * * * * clk_out<='0';
> > * * * * cnt:=0;
> > elsif rising_edge(clk) then
> > * * * * if (cnt=divider_half-1) then
> > * * * * * * * * clk_out<=NOT(clk_out);
> > * * * * * * * * cnt:=0;
> > * * * * else
> > * * * * * * * * cnt:=cnt+1;
> > * * * * end if;
> > end if;
> > end process;

>
> > Note that divider_half is X/2.

>
> > The code is not tested - just written in the mail program.

>
> > Ralf

>
> However the syntax check gives an error message:
>
> Parameter clk_out of mode out can not be associated with a formal
> parameter of mode in.
>
> for the line:
> clk_out<=NOT(clk_out);- Hide quoted text -
>
> - Show quoted text -


You can not have a port of mode "out" being assigned to another
signal. That makes sense if you think in terms of hardware, doesn't
it?

I can give you two solutions:
1. Change the mode of clk_out to "inout."
2. A better solution would be to declare an internal signal and assign
it to clk_out after the process. For example,

signal clk_sig : std_logic;
process(reset_n,clk)
variable cnt : integer;
begin
if (reset_n='0') then
clk_sig<='0';
cnt:=0;
elsif rising_edge(clk) then
if (cnt=divider_half-1) then
clk_sig<=NOT(clk_sig);
cnt:=0;
else
cnt:=cnt+1;
end if;
end if;
end process;

clk_out <= clk_sig;

 
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