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hi, all,
this describes a logic_vector to integer converter function.
and I comiple it in maxplusII student edition, but I found an error:
"unsupported feature error: a deferred constant declaration without a
full declaration is not supported"
but while I synthesis it in quartusII 5.1sp1, it success...

so what's wrong in maxplusII student editon? it's about packages
supported? or something else?

thanks.
follow is the code section:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity vectorToInt is
port(
vector : in std_logic_vector(4 downto 0);
int : out integer range 0 to 31
);
end entity vectorToInt;

architecture behave of vectorToInt is
function VIConvert(vectorIn : std_logic_vector(4 downto 0)) return
integer is
variable intOut : integer;
variable temp : integer;
begin
intOut := 0;
for i in 0 to 4 loop
temp := 1;
if vectorIn(i) = '1' then
if i = 0 then
intOut := intOut + 1;
else
for j in 1 to i loop
temp := temp * 2;
-- since maxplusII student edition doesn't support operator
**, just use * instead here.
end loop;
intOut := intOut + temp;
end if;
elsif vectorIn(i) = '0' then
intOut := intOut;
else
intOut := 0;
end if;
end loop;
return intOut;
end function VIConvert;

signal vectorIn : std_logic_vector(4 downto 0);
begin
vectorIn <= vector;
process(vectorIn)
begin
int <= VIConvert(vectorIn);
end process;
end behave;

and another problem:
sometimes in maxplusII student edition, while compile, an error point
to varialbe defination in function part. error message as follow:
non locally static bounds are not supported.

but it is also disappeared if I synthesis the code in quartusII.
what's wrong with maxplusII ... I really can't find them...

thanks!

-- Noah

Noah wrote:

> this describes a logic_vector to integer converter function.

Why do you need this?

With IEEE.Numeric_std you can simply use:

my_int<=to_integer(unsigned(my_std_logic_vector));
my_int<=to_integer(signed(my_std_logic_vector));


Even with std_logic_arith a similar way of conversion exists.
Nevertheless std_logic_arith as well as std_logic_unsigned are *not*
recommended, because they are not standard functions.

Ralf

Noah wrote:

> what's wrong with maxplusII ... I really can't find them...

MAXplus2 is obsolete and unusable for vhdl synthesis.
Try the free version of quartus here.
http://www.altera.com/products/softw...arwebmain.html

-- Mike Treseler

yeah, I know some functions come with libraries

but I just learn about sub programs. and unfortunately, just encoutner such
problems... and want to know the solution ...

thanks!

-- Noah

"Ralf Hildebrandt" <Ralf->
??????:...
> Noah wrote:
>
>> this describes a logic_vector to integer converter function.
>
> Why do you need this?
>
> With IEEE.Numeric_std you can simply use:
>
> my_int<=to_integer(unsigned(my_std_logic_vector));
> my_int<=to_integer(signed(my_std_logic_vector));
>
>
> Even with std_logic_arith a similar way of conversion exists. Nevertheless
> std_logic_arith as well as std_logic_unsigned are *not* recommended,
> because they are not standard functions.
>
> Ralf

yeah. I have also used quartusII to synthesis the code. it's totally ok.
but for some reasons, I have to use maxplusII student edition... so...

thanks!

--Noah

"Mike Treseler" <>
??????:...
> Noah wrote:
>
>> what's wrong with maxplusII ... I really can't find them...
>
> MAXplus2 is obsolete and unusable for vhdl synthesis.
> Try the free version of quartus here.
> http://www.altera.com/products/softw...arwebmain.html
>
> -- Mike Treseler