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Verilog Task Call with VHDL TestBench

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anyone know how I could call a verilog task through a VHDL Testbench?
I have a protected Verilog modul with an VHDL interface. I have built a
Tesbench in VHDL. But now I need also to call the task in the protected
I think in Verilog Testbench would do it so:

And in VHDL???

Thank you very much.


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