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help vhdl code plz

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hi everyone,
I am trying to develop vhdl code for this problem.It's an 8 bit shift
register.when chip select is high and clk is low then the input data is
fed to the shift register.D7 is the first bit to enter into the register
and also the first bit to come as an output.the output should be displaced
at the falling edge of teh clk.plz help me with this.thanx in advance

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