design compiler optimization

Hi,

Does synopsys design compiler perform a TILOS based circuit
optimization.

TILOS is a iterative circuit sizing tool which selects the critical
path and finds the sensitive gate in the path sizes it and then
continues with the new critical path, published in 1985 by fishburn and
dunlop.

any information and details about this is requested.

if yes, Also can anyone tell me the set of commands to do the
optimization.

thanks,

Mahalingam

mahalingamv@gmail.com