New Commer

Hi,

I am new to FPGA design and my questions will be very basic. I hope i
won't upset you gurus.....

Q1. How do you capture a signal comming from outside on the FPGA pin.
Obviously the data comming from outside will have a stobe/clock
associated with it. What are the methods that the data from out side
world will be clocked in with FPGA clock.

Q2. Once the data captured where does it go. Is it stored in the IP
registers or it is transfered to RAM. If it is to be transfered how the
IP (capture the data) will know where to put the data. I mean the
address of location.

Q3. Each user IP should have its own address where this address is
stored.

I apperitiate your help

Thanks

faraz.khan@nssi.us

wrote:
> I am new to FPGA design and my questions will be very basic. I hope i
> won't upset you gurus.....
>
> Q1. How do you capture a signal comming from outside on the FPGA pin.
> Obviously the data comming from outside will have a stobe/clock
> associated with it. What are the methods that the data from out side
> world will be clocked in with FPGA clock.

Depends on the application, really. Some data signals are synchronous
to a clock; some aren't. Some signals are accompanied by a data valid
signal; some aren't. Some signals are on a tri-state bus; some aren't.
Some signals are multiplexed onto a single pin; some aren't.

> Q2. Once the data captured where does it go. Is it stored in the IP
> registers or it is transfered to RAM. If it is to be transfered how the
> IP (capture the data) will know where to put the data. I mean the
> address of location.

Depends on the application, really. What do you want to do with the
data?

> Q3. Each user IP should have its own address where this address is
> stored.

Depends on the application, the IP and what it will do with the data,
really.

My answers are as vague as your questions.

-a

Andy Peters

First thanks for replying....

Well let me put my questions in more clear form...

I am new to FPGA development. I wanted to attach a A/D to Xilinx
Virtex4FPGA over the SPI bus. Now i guess SPI communication is
synchronous so i would have a clock attached to data. Once i receive
this clock and data at the pin. What are my next steps???? I can use
shift registers to record the data or FIFO???? Once i have this data
available in register using PLB bus i want to transfer this to BRAM so
processor can read it and can be shared with rest of user logic.

To be more simple i can have discrete comming into FPGA with data
valid. What are my options .. How to take it and put it in BRAM so can
be shared with rest of user logic.

Thanks

Faraz

faraz.khan@nssi.us

wrote:


> I wanted to attach a A/D to Xilinx
> Virtex4FPGA over the SPI bus. Now i guess SPI communication is
> synchronous so i would have a clock attached to data.

You need an SPI communication component - some black box, that speaks SPI.


> Once i receive
> this clock and data at the pin. What are my next steps????

You communicate with the SPI black box. Once you have a SPI component it
is clear how to interface it. How to do this strongly depends on the
black box. If it is a very smart box and does SPI communication without
any need of help by other components, you just read from / write to the
black box the data if the box has signaled you, that it is ready.

If you don't have such a black box, you need to build one for yourself.
Because such a box has to communicate with other components, you need to
design an interface. You need a data bus (one signal for input and one
for output direction) and some control signals. If you want to have an
example search for the "MSSP Interface" for the Microchip PIC. This is a
SPI component for this 8 bit microcontroller.


> Once i have this data
> available in register using PLB bus i want to transfer this to BRAM so
> processor can read it and can be shared with rest of user logic.

Take a look at the MSSP interface. If your main operating machine is a
processor it may fit good.

(The MSSP is designed to be located in RAM address space of an
microcontroller. Although it is designed for the PIC, I've written such
a component with an interface to the microcontroller MSP430. So adaption
is possible. (May I note, that it is available as an IP-core at my
company?))


> To be more simple i can have discrete comming into FPGA with data
> valid. What are my options .. How to take it and put it in BRAM so can
> be shared with rest of user logic.

Your approach of writing the data to the RAM and reading it is also
possible, but nevertheless you need a component that grants access to
the RAM either for the SPI-communication component or for your CPU - or
you need a dual-port RAM. (Dual-port RAMs are available, but remember,
if you need to add another component you will not find a triple-port
RAM. So it might be a good idea to create a RAM-bus arbiter.)

Ralf

Ralf Hildebrandt