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VHDL - Verilog, PSL or SystemVerilog of OVL? |
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03-27-2006, 03:09 PM
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#1 |
Verilog, PSL or SystemVerilog of OVL?
Hi all,
I am a Verilog user. I want to use assertion based verification in my project. And I found OVL(Open Verification library). Do you think which one of the OVL is better? Verilog, PSL or SystemVerilog? And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in SystemVerilog again? Best regards, Davy Davy |
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03-28-2006, 09:37 AM
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#2 |
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Posts: n/a
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Re: Verilog, PSL or SystemVerilog of OVL?
I'd recommend you to go for SystemVerilog, as it's the hardware
language of the future. Joe, LogicSim - Your Personal Verilog Simulator http://www.logicsim.com Davy wrote: > Hi all, > > I am a Verilog user. > I want to use assertion based verification in my project. And I found > OVL(Open Verification library). > > Do you think which one of the OVL is better? Verilog, PSL or > SystemVerilog? > > And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in > SystemVerilog again? > > Best regards, > Davy ngsayjoe@gmail.com |
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03-28-2006, 10:34 AM
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#3 |
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Posts: n/a
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Re: Verilog, PSL or SystemVerilog of OVL?
hi,
I recommend system verilog .its more powerful and therefore a little hard to learn. With system verilog you can write your own assertions better than the predefined ones. PSL is almost same as System Verilog Assertions regards, Amupam Jain anupam |
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