Arrays of real in the port declaration

Hi,

I'm trying to write a simple grammar for VHDL and I'm stuck on how to
declare an array of real numbers in the port declaration. Why is it that the
straightforward representation [2] similar to the one used using bit_vector
[1] doesn't work? How should it be declared? Is there an elegant way around
it besides listing all the elements in the port declaration, for instance,
d0, d1, d2, d3?


[1]:
entity myModel is
port (d: in bit_vector (0 to 3);
result: out bit);
end myModel;


[2]:
entity myModel is
port (d: in array (0 to 3) of real;
result: out real);
end myModel;


Many thanks.

Candida

---
Candida Ferreira, Ph.D.
Chief Scientist, Gepsoft
http://www.gene-expression-programming.com/author.asp

GEP: Mathematical Modeling by an Artificial Intelligence
(Springer Verlag edition 2006)
http://www.gene-expression-programmi...ooks/index.asp
Online Version:
http://www.gene-expression-programmi...troduction.htm

Modeling Software:
http://www.gepsoft.com/

Candida Ferreira

Candida Ferreira wrote:
> Hi,
>
> I'm trying to write a simple grammar for VHDL and I'm stuck on how to
> declare an array of real numbers in the port declaration. Why is it that the
> straightforward representation [2] similar to the one used using bit_vector
> [1] doesn't work? How should it be declared? Is there an elegant way around
> it besides listing all the elements in the port declaration, for instance,
> d0, d1, d2, d3?

Normally I would have a package file for the project with a declaration
like:
type RealArr_Type is array (0 to 3) of real;

Then use that in the port declaration.

entity myModel is
port (d: in RealArr_Type;
result: out real);
end myModel;

Duane Clark

Try...
type arr_Reals is array <> of real; -- Defines a new type called
'arr_Reals' which is an array of reals (size is not yet determined).
entity myModel is
port (d: in arr_Reals(0 to 3); -- Defines 'd' to be an array of 4
reals....indexed from 0 to 3
result: out bit);
end myModel;

KJ

"Candida Ferreira" <> wrote in message
news:TMdVf.122084$ .uk...
> Hi,
>
> I'm trying to write a simple grammar for VHDL and I'm stuck on how to
> declare an array of real numbers in the port declaration. Why is it that
> the straightforward representation [2] similar to the one used using
> bit_vector [1] doesn't work? How should it be declared? Is there an
> elegant way around it besides listing all the elements in the port
> declaration, for instance, d0, d1, d2, d3?
>
>
> [1]:
> entity myModel is
> port (d: in bit_vector (0 to 3);
> result: out bit);
> end myModel;
>
>
> [2]:
> entity myModel is
> port (d: in array (0 to 3) of real;
> result: out real);
> end myModel;
>
>
> Many thanks.
>
> Candida
>
> ---
> Candida Ferreira, Ph.D.
> Chief Scientist, Gepsoft
> http://www.gene-expression-programming.com/author.asp
>
> GEP: Mathematical Modeling by an Artificial Intelligence
> (Springer Verlag edition 2006)
> http://www.gene-expression-programmi...ooks/index.asp
> Online Version:
> http://www.gene-expression-programmi...troduction.htm
>
> Modeling Software:
> http://www.gepsoft.com/
>
>

KJ

Duane Clark wrote:
> Normally I would have a package file for the project with a declaration
> like:
> type RealArr_Type is array (0 to 3) of real;
>
> Then use that in the port declaration.
>
> entity myModel is
> port (d: in RealArr_Type;
> result: out real);
> end myModel;

That was really helpful; thank you so much Duane and KJ. The kind of code
I'm trying to generate automatically using APS is shown below:

library IEEE;

use ieee.math_real.all;



package apsModelTypes is

type RealArr_Type is array (0 to 3) of real;

end apsModelTypes;



use work.apsModelTypes.all;



entity apsModel is

port (d: in RealArr_Type;

result: out real);

end apsModel;



architecture apsGeneratedCode of apsModel is



function apsOR1(x, y: real) return real is

begin

if (x < 0.0 or y < 0.0) then

return 1.0;

else

return 0.0;

end if;

end apsOR1;



begin



geneConcatenation: process(d)

constant g1c1: real := 2.5;

constant g1c2: real := -2.3;

variable varTemp: real := 0.0;

begin

varTemp := apsOR1(d(1),d(3));

varTemp := varTemp + (-((d(1) / d(0))));

varTemp := varTemp + (-(((d(2) * (d(3) + d(1))) - d(2))));

varTemp := (g1c1 - d(3));

result <= varTemp;

end process geneConcatenation;



end apsGeneratedCode;





Thanks again.

Candida

Candida Ferreira