Verilog Task pass value problem?

Hi all,

I am reading the book "Writing Testbench". And write the code below:
It seems the code is blocked in the task "@ (posedge clk)", and the
task never return the "valid", why?
I guess task cannot pass the continuous clk value?

//--------test.v-------------
module test;

reg clk;
integer i;
reg [7:0] input1,input2;
reg [7:0] valid1;

test_lib test_lib();

always begin
#50 clk <= 1'b0;
#50 clk <= 1'b1;
end

initial begin
for (i=1;i<=8;i=i+1)
begin
input1 = i;
input2 = i;
begin
test_lib.compare_vector(clk,input1,input2,valid1);
end
@ (posedge clk);
end
end

endmodule
//---------end test.v--------------

//----------test_lib.v-------------
module test_lib;

task automatic compare_vector;
input clk;
input [7:0] input1;
input [7:0] input2;
output valid;
begin
$write("p1\n");
@ (posedge clk)
valid = (input1==input2);
$write("p2\n");
end
endtask
endmodule
//-------end test_lib.v------------

Any suggestions will be appreciated!
Best regards,
Davy

Davy

Task arguments are passed by value and hence is what you have
seen/observed. Your option will be to pass the clk as input to test_lib
module.

HTH
Ajeetha, CVC
www.noveldv.com

Ajeetha

Hi Ajeetha,

If I pass clk to test_lib, shall I use `include "test_lib.v"?

Best regards,
Davy

Davy

Davy,
That wouldn't change from the way you currently compile it. Say:

vcs test_lib.v test.v

Only the instantiation changes:

>>test_lib test_lib();
test_lib test_lib(.clk(clk));

HTH
Ajeetha CVC
www.noveldv.com

Ajeetha

Hi Ajeetha,

All OK, thank you!

Best regards,
Davy

Davy