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How to stop simulation in VHDL?

 
 
savitha.john@gmail.com
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      03-24-2006
I want to stop the simulation in between for VHDL.
Is there any construct similar to $finish( in verilog)

 
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Mike Treseler
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      03-24-2006
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
> I want to stop the simulation in between for VHDL.
> Is there any construct similar to $finish( in verilog)


Not exactly.
Find "done_s" and "coda" in this page for
an example of forcing all processes to wait:

http://home.comcast.net/~mike_treseler/

The other way is to force an assertion failure,
but I don't like seeing failure warnings
when the testbench passes.

-- Mike Treseler
 
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Weng Tianxiang
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      03-25-2006
When running ModelSim before loading project, clike menu: Simulate,
click Runtime Option, set Default run time data you want: for example,
200us, then click Apply

After project is loaded, you must have known everything else to do.

Each time you run your simulation, ModelSim will stop after the
simulation time is finished.

No coding is required.

Weng

 
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kulkarku@math.net
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      03-27-2006
Hi,
u can use "break" commadn on vsim prmpt of the modelsim.

 
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kulkarku@math.net
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      03-27-2006
Hi,
u can use "break" commadn on vsim prmpt of the modelsim.

 
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savitha.john@gmail.com
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      03-27-2006
Thank you all.........I am using ncsim for simulation...and that too ,a
command line interface....
I have implemented an assertion failure as Mike said....That did
work...But still ..even I don't like seeing failure warnings
when the testbench passes.......

Thanks a lot Mike

 
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Petrov_101@hotmail.com
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      03-31-2006

(E-Mail Removed) wrote:
> Thank you all.........I am using ncsim for simulation...and that too ,a
> command line interface....
> I have implemented an assertion failure as Mike said....That did
> work...But still ..even I don't like seeing failure warnings
> when the testbench passes.......
>
> Thanks a lot Mike


I don't like seeing failure warnings either...

I use the following syntax to end the simulation:
assert false report "NONE. End of simulation." severity
failure;

The simulator then outputs the following:
# ** Failure: NONE. End of simulation.

Not a perfect solution but works for me...

Pete

 
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jtw
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      04-01-2006
A method I sometimes use is having all clocks 'automatically' stop
(typically, sometime after a stimulus input file has finished); when there
are no more processes pending, the simulation will stop.

Alternatively, sometimes I call the simulation with a generic limiting the
amount of time.

JTW

<(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
>
> (E-Mail Removed) wrote:
>> Thank you all.........I am using ncsim for simulation...and that too ,a
>> command line interface....
>> I have implemented an assertion failure as Mike said....That did
>> work...But still ..even I don't like seeing failure warnings
>> when the testbench passes.......
>>
>> Thanks a lot Mike

>
> I don't like seeing failure warnings either...
>
> I use the following syntax to end the simulation:
> assert false report "NONE. End of simulation." severity
> failure;
>
> The simulator then outputs the following:
> # ** Failure: NONE. End of simulation.
>
> Not a perfect solution but works for me...
>
> Pete
>



 
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Hans
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      04-01-2006
For those of you that are using Modelsim you can simple add a signal to your
testbench and assert this signal at the end of the simulation. Then use the
"when" statement in your script to stop the simulator.

Example: stop Modelsim when the signal end_of_simulation='1'

when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"
; stop ;}

# End of simulation
# Simulation stop requested

Let hope accellera will sort this out for SystemVHDL....HyperVHDL...or
whatever they are planning to call it (assuming of course they are still
actively working on it...)

Hans
www.ht-lab.com


<(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
>I want to stop the simulation in between for VHDL.
> Is there any construct similar to $finish( in verilog)
>




 
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