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VHDL - why can not signal be assigned asscess type? |
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03-23-2006, 09:43 PM
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why can not signal be assigned asscess type?
why can not signal be assigned asscess type?
I think the difference between signal and variable is only that the if we use signal the speed of simulation would be slower than we use variables,because signal needs more memory. But why signal can not be assigned access type? I think there should be some advantages for that. what are they then?: ) risingsunxy@googlemail.com |
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