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VHDL - help VHDL- verilog co simulation |
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03-23-2006, 04:42 AM
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#1 |
help VHDL- verilog co simulation
Hi
Can anybody tell me How to interface VHDL generic port map with verilog model? Thanks in advance absr |
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03-23-2006, 05:05 PM
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#2 |
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Posts: n/a
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Re: help VHDL- verilog co simulation
absr wrote:
> Can anybody tell me How to interface VHDL generic port map with > verilog model? http://groups.google.com/groups?q=mo...+vhdl+port+map Mike Treseler |
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12-24-2007, 10:07 AM
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#3 | |
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Junior Member
Join Date: Dec 2007
Posts: 1
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Quote:
I want to know that too, can anybody help, thanks! flyfish866 |
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