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about "tri-states data bus" problem

 
 
captain
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      01-05-2008
my module is as follows:

entity tri_state_bus is
Port ( data : inout STD_LOGIC_VECTOR (15 downto 0);
cs : in STD_LOGIC;
rd : in STD_LOGIC;
we : in STD_LOGIC;
clk: in STD_LOGIC;
din : in STD_LOGIC_VECTOR (15 downto 0);
dout : out STD_LOGIC_VECTOR (15 downto 0));
end tri_state_bus;

architecture dbus of tri_state_bus is
begin
process(clk)
begin
if(clk'event and clk='1') then
if(cs='1') then
data<=(others=>'Z');
elsif(rd='0') then
data<=din;
elsif(we='0') then
dout<=data;
end if;
end if;
end process;
end dbus;
------------------
the problem is: i can synthesis by ISE/XST,but i can't obtain the
correct results when simulated using modelsim, can anyone tell me
where is the problem?
 
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Mike Treseler
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      01-05-2008
captain wrote:

> entity tri_state_bus is
> Port ( data : inout STD_LOGIC_VECTOR (15 downto 0);
> cs : in STD_LOGIC;
> rd : in STD_LOGIC;
> we : in STD_LOGIC;
> clk: in STD_LOGIC;
> din : in STD_LOGIC_VECTOR (15 downto 0);
> dout : out STD_LOGIC_VECTOR (15 downto 0));
> end tri_state_bus;


> the problem is: i can synthesis by ISE/XST,but i can't obtain the
> correct results when simulated using modelsim, can anyone tell me
> where is the problem?


I don't know what results you expect.
Your bus has separate data in and data out
which does not require tri-state buffers.

-- Mike Treseler

 
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Duane Clark
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      01-05-2008
captain wrote:
> my module is as follows:
> ...
> ------------------
> the problem is: i can synthesis by ISE/XST,but i can't obtain the
> correct results when simulated using modelsim, can anyone tell me
> where is the problem?


You have not said what you think the "correct" results are, and what you
are getting instead.
 
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Geno
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      02-02-2008
captain wrote:
> my module is as follows:
>
> entity tri_state_bus is
> Port ( data : inout STD_LOGIC_VECTOR (15 downto 0);
> cs : in STD_LOGIC;
> rd : in STD_LOGIC;
> we : in STD_LOGIC;
> clk: in STD_LOGIC;
> din : in STD_LOGIC_VECTOR (15 downto 0);
> dout : out STD_LOGIC_VECTOR (15 downto 0));
> end tri_state_bus;
>
> architecture dbus of tri_state_bus is
> begin
> process(clk)
> begin
> if(clk'event and clk='1') then
> if(cs='1') then
> data<=(others=>'Z');
> elsif(rd='0') then
> data<=din;
> elsif(we='0') then
> dout<=data;
> end if;
> end if;
> end process;
> end dbus;
> ------------------
> the problem is: i can synthesis by ISE/XST,but i can't obtain the
> correct results when simulated using modelsim, can anyone tell me
> where is the problem?


It looks like you are trying to model some kind of D flip-flop, so here
is my try:

entity tri_state_bus is
Port (
cs : in STD_LOGIC;
rd : in STD_LOGIC;
we : in STD_LOGIC;
clk: in STD_LOGIC;
din : in STD_LOGIC_VECTOR (15 downto 0);
dout : out STD_LOGIC_VECTOR (15 downto 0));
end tri_state_bus;




architecture dbus of tri_state_bus is
begin
data: STD_LOGIC_VECTOR (15 downto 0); -- make data a local (not a port) signal.
process(clk)
begin
if(clk'event and clk='1') then
elsif(we ='0' and cs = '0') then -- clock enable?
data<=din;
end if;
end if;
if (rd='0' and cs = '0') then -- output enable?
dout<=data;
else
data<=(others=>'Z');
end if;
end process;
end dbus;


Regards,

Geno
 
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Andy
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      02-04-2008
On Feb 2, 11:56 am, Geno <(E-Mail Removed)> wrote:
> captain wrote:
> > my module is as follows:

>
> > entity tri_state_bus is
> > Port ( data : inout STD_LOGIC_VECTOR (15 downto 0);
> > cs : in STD_LOGIC;
> > rd : in STD_LOGIC;
> > we : in STD_LOGIC;
> > clk: in STD_LOGIC;
> > din : in STD_LOGIC_VECTOR (15 downto 0);
> > dout : out STD_LOGIC_VECTOR (15 downto 0));
> > end tri_state_bus;

>
> > architecture dbus of tri_state_bus is
> > begin
> > process(clk)
> > begin
> > if(clk'event and clk='1') then
> > if(cs='1') then
> > data<=(others=>'Z');
> > elsif(rd='0') then
> > data<=din;
> > elsif(we='0') then
> > dout<=data;
> > end if;
> > end if;
> > end process;
> > end dbus;
> > ------------------
> > the problem is: i can synthesis by ISE/XST,but i can't obtain the
> > correct results when simulated using modelsim, can anyone tell me
> > where is the problem?

>
> It looks like you are trying to model some kind of D flip-flop, so here
> is my try:
>
> entity tri_state_bus is
> Port (
> cs : in STD_LOGIC;
> rd : in STD_LOGIC;
> we : in STD_LOGIC;
> clk: in STD_LOGIC;
> din : in STD_LOGIC_VECTOR (15 downto 0);
> dout : out STD_LOGIC_VECTOR (15 downto 0));
> end tri_state_bus;
>
> architecture dbus of tri_state_bus is
> begin
> data: STD_LOGIC_VECTOR (15 downto 0); -- make data a local (not a port) signal.
> process(clk)
> begin
> if(clk'event and clk='1') then
> elsif(we ='0' and cs = '0') then -- clock enable?
> data<=din;
> end if;
> end if;
> if (rd='0' and cs = '0') then -- output enable?
> dout<=data;
> else
> data<=(others=>'Z');
> end if;
> end process;
> end dbus;
>
> Regards,
>
> Geno


I'm pretty sure synthesis tools will either not synthesize that, or if
they do, the HW will not behave like the RTL.

The only tools that I am aware of that will accept assignments after
the clocked if clause in a clocked process, all work only with signals
assigned from an expression of (or under conditions of) variables
assigned within the clocked clause, or with regards to an asynchronous
reset functionality (where maybe not all signals assigned in the
clocked clause are affected by reset), in which case the values
assigned must be static.

Many synthesis tools allow a synchronous assignment to 'Z', which
usually (depends on target arch) results in a register for the data, a
tri-state buffer and a register for the enable on that TS buffer.

Andy
 
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