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-- multiD-vhdl: Multidimensional Array (allowing generics) for VHDL
-- ================================================== ==============
-- Version 1.0 (20 March 2006)



-- *** Package Purpose:
-- Multidimensional Arrays with complete control of every dimension;
-- allowing every dimension to be specified with generics
-- (especially useful for multi-dimensional parametizable ports)

-- *** How is it implemented?
-- As a 1-dimensional array, that is treated as a multi-dimensional
-- array


-- *** Why?
-- VHDL (VHSIC Hardware Description Language) lacks the possiblity
-- to define multidimensional arrays for ports,
-- ###where each dimension can be kept generic###.

-- It was not possible (with normal VHDL) to have multiple instances of
-- an entity,
-- ###where each instance can have different generics for each
-- dimension###.

-- This can be solved with this VHDL package (with functions), that
-- allows a 1D array to be treated as a multidimensional array.


-- *** Is it synthesizable?
-- Yes: has been tested on Synplify 8.5 (tested entity: generic MUX)




Get it here:
http://stud4.tuwien.ac.at/~e0425408/...ultiD-vhdl.zip

License:
LGPL


Comments, Suggestions welcome




=============================================
Albert Neumüller
21 March 2006
=============================================








-------------------------------------------------------------------------------
-- QUICK Usage Examples:
-- Requires fixed-width font (courier, etc.)
--
-- 1. Initializtion
--
-- Example: 3D - array
-- --we want: %%% (0 to 6, 4 downto 2, 1 to %%% -------->
--
-- constant dim_info : DD_dimensions := (0, 6, 4, 2, 1, ;
-- -- |--| |--| |--|
-- -- dim0 dim1 dim2
--
-- signal arr3D : std_logic_vector(DD_zero to
DD_calc_size(dim_info)-1);
--
--
-- 2. Accessing sub-parts of the multiD (multi-dimensional) array:
--
-- Example:
-- signal result : std_logic_vector(1 to ;
--
-- --we want: %%% result <= arr3D(3 to 3, 2 to 2, 1 to %%%
-------->
--
-- result <= DD_slice(dim_info, (3, 3, 2, 2, 1, , arr3D);
-- -- |--| |--| |--|
-- -- dim0 dim1 dim2
--
--
-- 2. Accessing sub-parts of the multiD array:
--
-- Example:
-- variable assign_v : std_logic_vector(7 downto 0);
--
-- --we want: %%% arr3D(3 to 3, 2 to 2, 1 to <= assign_v;
--
-- DD_assign2slice(dim_info, (3, 3, 2, 2, 1, , arr3D, assign_v);
-- -- |--| |--| |--|
-- -- dim0 dim1 dim2

-- *** Why?
-- VHDL (VHSIC Hardware Description Language) lacks the possiblity
-- to define multidimensional arrays for ports,
-- ###where each dimension can be kept generic### & where it is
synthesizable.

-- It was not possible (with normal VHDL) to have multiple instances of
-- an entity,
-- ###where each instance can have different generics for each
-- dimension### & syntheziable.


=============================================
Albert Neumüller
21 March 2006
=============================================

Albert,
Fortunately arrays of unconstrained arrays will
be a supported feature of the Accellera VHDL-2006 revision.
Make sure your vendors know that you want it supported.

Cheers,
Jim

> -- multiD-vhdl: Multidimensional Array (allowing generics) for VHDL
> -- ================================================== ==============
> -- Version 1.0 (20 March 2006)
>
>
>
> -- *** Package Purpose:
> -- Multidimensional Arrays with complete control of every dimension;
> -- allowing every dimension to be specified with generics
> -- (especially useful for multi-dimensional parametizable ports)
>
> -- *** How is it implemented?
> -- As a 1-dimensional array, that is treated as a multi-dimensional
> -- array
>
>
> -- *** Why?
> -- VHDL (VHSIC Hardware Description Language) lacks the possiblity
> -- to define multidimensional arrays for ports,
> -- ###where each dimension can be kept generic###.
>
> -- It was not possible (with normal VHDL) to have multiple instances of
> -- an entity,
> -- ###where each instance can have different generics for each
> -- dimension###.
>
> -- This can be solved with this VHDL package (with functions), that
> -- allows a 1D array to be treated as a multidimensional array.
>
>
> -- *** Is it synthesizable?
> -- Yes: has been tested on Synplify 8.5 (tested entity: generic MUX)
>
>
>
>
> Get it here:
> http://stud4.tuwien.ac.at/~e0425408/...ultiD-vhdl.zip
>
> License:
> LGPL
>
>
> Comments, Suggestions welcome
>
>
>
>
> =============================================
> Albert Neumüller
> 21 March 2006
> =============================================
>
>
>
>
>
>
>
>
> -------------------------------------------------------------------------------
> -- QUICK Usage Examples:
> -- Requires fixed-width font (courier, etc.)
> --
> -- 1. Initializtion
> --
> -- Example: 3D - array
> -- --we want: %%% (0 to 6, 4 downto 2, 1 to %%% -------->
> --
> -- constant dim_info : DD_dimensions := (0, 6, 4, 2, 1, ;
> -- -- |--| |--| |--|
> -- -- dim0 dim1 dim2
> --
> -- signal arr3D : std_logic_vector(DD_zero to
> DD_calc_size(dim_info)-1);
> --
> --
> -- 2. Accessing sub-parts of the multiD (multi-dimensional) array:
> --
> -- Example:
> -- signal result : std_logic_vector(1 to ;
> --
> -- --we want: %%% result <= arr3D(3 to 3, 2 to 2, 1 to %%%
> -------->
> --
> -- result <= DD_slice(dim_info, (3, 3, 2, 2, 1, , arr3D);
> -- -- |--| |--| |--|
> -- -- dim0 dim1 dim2
> --
> --
> -- 2. Accessing sub-parts of the multiD array:
> --
> -- Example:
> -- variable assign_v : std_logic_vector(7 downto 0);
> --
> -- --we want: %%% arr3D(3 to 3, 2 to 2, 1 to <= assign_v;
> --
> -- DD_assign2slice(dim_info, (3, 3, 2, 2, 1, , arr3D, assign_v);
> -- -- |--| |--| |--|
> -- -- dim0 dim1 dim2
>


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~