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VHDL - Using Prime Time To Find All The Paths Of A Seq. Cir., Not Only the Critical Ones |
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Hi All,
I would like to use Synopsys's Prime Time in my research in path delay analysis. I have ITC benchmark files given in vhd format which are sequential logic circuits. I would like to find all the paths of a benchmark using synopsys. First, I use design analyzer to convert behavioral vhd to structural verilog format. Here, I want prime time to find all the paths, not only the critical ones. When I look at the write_delay_paths command of P.T., there is a slack option. With this option, it should write paths with slack less than the specified crit_time. The default says it is infinite. What I am hoping is with this default option, I should get the critical paths, plus with an infinite slack the rest of them. If I can achieve it, I will feed the benchmark with all paths to Tetra-max in order to create test vectors. If anybody can help me to find all the paths by using prime time, it would be a great help in my research. Regards, Ilteris Murat Derici Southern Methodist University Ph.D. Student ilterisderici@hotmail.com |
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