Urgent Help for xilinx Synthesizing

Hi Friends

Friends, i have been struggling for 1.5 months on a problem.Let me
explain u a little bit.

I am working on FPGA implementation of Dijkstra's Shortest Path
Algorithm on XILINX 7.1 ISE.Now I hav implemented the code in
verilog.The Number of nodes in my case is 256(IF U REQUIRE MY CODE I
WILL SEND IT).The tragedy is that the code is working fine but when i m
synthesizing it it is giving the following error which i am unable to
resolve.

The error is "
Portability:3 - This Xilinx application has run out of memory or has
encountered a memory conflict. Current memory usage is 1869512 kb.
Memory problems may require a simple increase in available system
memory, or possibly a fix to the software or a special workaround. To
troubleshoot or remedy the problem, first: Try increasing your system's
RAM. Alternatively, you may try increasing your system's virtual memory
or swap space. If this does not fix the problem, please try the
following: Search the Answers Database at support.xilinx.com to locate
information on this error message. If neither of the above resources
produces an available solution, please use Web Support to open a case
with Xilinx Technical Support off of support.xilinx.com. As it is
likely that this may be an unforeseen problem, please be prepared to
submit relevant design files if necessary.
ERROR: XST failed"

My verilog code consists of following operations:
1)Calulating the adjecancy Matrix and Path Matrix.
2)Recursive Algorithm using Task (Palnitkar says that Task and Function
is Synthesizable).

Also let me inform u that my code is 100% behavorial.

While synthesizing It shows "Enabling Task " for 8 hrs and then shows
above error.
If u know anything about the above error please tell me as the deadline
is approaching fastly for project submission.

Looking for ur help
Thanx
Saroj
mail me at:

coolsaroj@gmail.com

I suspect you are running ISE under Windows. There is a memory limit
for applications on windows OS. This limit is normally 2GBytes. And
from the number you gave me it seems the Xilinx mapper runs out of
memory. You have a number of choices. Once is to increase the
application limit for windows to 3GB or use Linux/Unix flavours
instead.

Here is a link to Micrsosoft description of this switch
http://tinyurl.com/aublu. Off course you need to have at least 4GB of
memory to set aside 3GB to applications.

I have seen this when I sue -timing for mapper, but not XST! You can
try Synplify as well if you have access to it.

I am curious about your code as well. How complicated is it? Could
you send it to me to check?

-- Amal

Amal

Thank u Amal
Can u give me ur email id on which i can send u my code as well as
TestBench?my mail id is .
Thank u

coolsaroj@gmail.com

Hello friends
I changed the memory space to 3GB,still after a long time xilinx
popped up with the same error which I mentioned.The No. of nodes in
graph was 256 which I think is quite huge.

Then I reduced the no. of nodes in graph to 16.Now it is showing
"Unsupported recursivity".Can anybody suggest what to do for fix this
problem?For any clarification please post your quiery here.
Thank you

Chauhan

schrieb:
> I am working on FPGA implementation of Dijkstra's Shortest Path

So i guess you wrote a SW like code, no HW description.

> My verilog code consists of following operations:
> 1)Calulating the adjecancy Matrix and Path Matrix.
> 2)Recursive Algorithm using Task (Palnitkar says that Task and Function
> is Synthesizable).
>
> Also let me inform u that my code is 100% behavorial.

Behavioral code is not intended to synthesis. It may synthesis well,
but it doesn't need to.
Without seeing your code I expect you use some constructs which will
lead to massive HW leading to enormous need of RAM to work on the
design.
eg:
signal a,b,c : sts_logic_vector(63 downto 0)
for i in 1 to 256 loop
A <= B + C * i; -- needs type conversions to work *g*
end for;

will lead to HW that consists of 256 adders and multipliers with 64 bit
width. You will find no HW that fits this amount and your tool will
calculate for years to find a solution fitting in
your device, especially if you also set timing constraints. Some simple
changes result in a code that inferrs only one adder, one multiplier
and a counter (taking 256 clock cycles to do the same job) which will
be no problem in most devices.

It is a common mistake for SW orientated developers to forget the
underlying HW. So the HW they describe does too many steps in one,
resulting in (too) massive parallel HW structures.

bye Thomas

Thomas Stanka

If you don't mind posting your code, we can comment on your code, other
than that, I can't help much.

-- Amal

Amal