Help

Hi there,
Really struggling with some VHDL code. Have been asked to write a high level VHDL model of a 16-word by 12 bit memory in which the contents of the memory are initialised by reading from a file.

The memory should have 5 address lines, 12 bi-directional, trisate data and an active low enable control. When enable is low the memory will read or write in accordance with the state of the read/write control. The read/write input is a single bit, 1 indicating read and 0 indicating write.

Any help would be great, really struggling here chaps.

craigs2