How is Synopsys DC 2004.06-SP2's capability in synthesizing large designs.

Hi, there:

My design is 350K gate in ASIC logic, however once I instantiated in 9
blocks
of ASIC RAM of various bits (ranging 2560~8192bits), the gate count DC
gave me was 600K. Now I am perparing for client's inquiries on whether such
design is too large for DC to handle in a top-down synthesis. Is it good to
tell
them the synthesis was OK?

My DC never gave me problems and synthesis time was quite acceptable.

Thanks in advance

Novice

Count only related modules. Make hierarchical report and check what is
the problem.

michaelst@gmail.com

<> wrote in message
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> Count only related modules. Make hierarchical report and check what is
> the problem.
>

Thank you. I think, there is no problem in the synthesis. Only that DC gives
a
tens of kilo-gate count to each of the RAMs which are instantiated. These
RAMs are pre-made and delivered as .db format.

I was aware that DC can handle designs up to 250K gates in top-down
synthesis.
Since the RAMs are 300K gates extra, and DC doesn't really optimize these
RAMs,
can I say that the design is nearly within the power of DC?

Novice

What do you mean by "power of DC"?

michaelst@gmail.com

<> wrote in message
news: ups.com...
> What do you mean by "power of DC"?
>

During trainings, I was told DC can handle designs up to 250K gates, if a
design is much
larger than that, it's advised to to hierarchical synthesis, meaning
synthesizing individual
modules then combine the netlist and do incremental synthesis.

Novice

Our designs are more than 500kGates (without memories). We are using DC
without any problems.

michaelst@gmail.com