verification

Hi,
I want to know basic about verification. I know VHDL lang. I am working
on a project in VLSI. I worked on xilinx webpack6.8, modelsim 5.8 &
leonardo spectrum.
Now i got a call for interview... which is for verification engineer.
please guide me what should I know about verification as I am preparing
for that. give me some general questions with hint answers.

Sarah

Sarah wrote:

> Now i got a call for interview... which is for verification engineer.
> please guide me what should I know about verification as I am preparing
> for that. give me some general questions with hint answers.


I would ask, "What exactly have you done with modelsim?"

I would suggest collecting and cleaning up examples
of your vhdl testbench code to show the interviewer.

Then practice running example testbenches from now
until the interview. Here's one:

http://groups.google.com/groups/sear...hell+test_uart

-- Mike Treseler

Mike Treseler

Sarah wrote:
> Hi,
> I want to know basic about verification. I know VHDL lang. I am working
> on a project in VLSI. I worked on xilinx webpack6.8, modelsim 5.8 &
> leonardo spectrum.
> Now i got a call for interview... which is for verification engineer.
> please guide me what should I know about verification as I am preparing
> for that. give me some general questions with hint answers.

I would expect that if you need a newsgroup to explain to you the
basics of verification, then you're not qualified for the position.
Don't waste the interviewer's time. Cancel the interview now.

-a

Andy Peters