Velocity Reviews > VHDL > Random Number Generation

# Random Number Generation

dpi
Guest
Posts: n/a

 03-13-2006
Hello,

I am using the UNIFORM function <UNIFORM(seed1, seed2, rand)> in my
VHDL code to generate random numbers.

Whether the seed are initialised to a particular number or left
uninitialised, for both cases, same sequence of random number are
generated every time I restart the simulation.

I suppose if I could start from an unknown, random state (generate a
random seed at the start of simulation), I could avoid this repetition
problem. In other languages, I have seen time of the day (which is
w.r.t. some date in the past) being used for this purpose. Do you know
how I could do it in VHDL??

Mike Treseler
Guest
Posts: n/a

 03-13-2006
dpi wrote:

> I am using the UNIFORM function <UNIFORM(seed1, seed2, rand)> in my
> VHDL code to generate random numbers.
> Whether the seed are initialised to a particular number or left
> uninitialised, for both cases, same sequence of random number are
> generated every time I restart the simulation.

Yes, that's how it works.

> I suppose if I could start from an unknown, random state (generate a
> random seed at the start of simulation), I could avoid this repetition
> problem. In other languages, I have seen time of the day (which is
> w.r.t. some date in the past) being used for this purpose. Do you know
> how I could do it in VHDL??

then calculate and save different values.

-- Mike Treseler

Amal
Guest
Posts: n/a

 03-13-2006
If you are using Modelsim, you can use the TCL build-in command rand()
to get a random number and use it as the seed. Or use [clock second]
or your own function to get a seed and pass it as a generic to your
VHDL.

quietly set seed1 [expr {int(1 + 2147483562*rand())}]; # [1,
2147483562]
quietly set seed2 [expr {int(1 + 2147483398*rand())}]; # [1,
2147483398]

quietly set options ""

eval vsim \$options -GgSEED1=\$seed1 -GgSEED2=\$seed2
ClockErrorCorrection_tb

-- Amal

Amal
Guest
Posts: n/a

 03-13-2006
If you are using Modelsim, you can use the TCL build-in command rand()
to get a random number and use it as the seed. Or use [clock second]
or your own function to get a seed and pass it as a generic to your
VHDL.

quietly set seed1 [expr {int(1 + 2147483562*rand())}]; # [1,
2147483562]
quietly set seed2 [expr {int(1 + 2147483398*rand())}]; # [1,
2147483398]

quietly set options ""

eval vsim \$options -GgSEED1=\$seed1 -GgSEED2=\$seed2 top_tb

-- Amal

vipinlal
Member
Join Date: Feb 2010
Posts: 39

 03-26-2010
The package you are using is not synthesizable.you can use this code instead:
vhdlguru.blogspot.com/2010/03/random-number-generator-in-vhdl.html