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Hallo everyone,now I have a question,what's the differences between the
behavioral model and the RTLmodel?

I am reading some source codes of a simple processor,it is a behavioral
model.
As I understand ,the behavior model just describes how the processor
behaves,
so it is not the description of the real circuits.Can this behavioral
model be synthesize?

And in these codes ,i see a lot of procedures are used.Are they typical
style of the behavioral descriptions?

Ok,waiting for your answers : )

Thanks

wrote:
> Hallo everyone,now I have a question,what's the differences between the
> behavioral model and the RTLmodel?

http://groups.google.com/groups/sear...model+RTL+vhdl

It is totally like your going to a restaraunt and give an order for one
dish.

If you order French Chicken, then the waiter will bring you a French
Chicken. That is behavioral model. You don't have to know all details.
Because its making is well known before you make an order.

If you describe a detailed list on what an chef needs to do or prepare
the dish:
1. Buy a new chicken;
2. Mix a French wine with it for a few minutes;
....
That is a RTL model.

What is the difference?

For a RTL model, you must be a professional chef who knows everything
to make a dish.
For a behavioral model, you don't have to know every details, but know
its name.

With a behavioral model of CPU, you can immediately learn a taste how a
CPU is designed, but miss every details of the design. That is
important to a beginner.

What an chip designer is doing everyday in a company is most likely a
RTL model.

Weng

Thank you very much !
so I think the behavioral model can not be syntheiszed ,right?
Or,if i want to design a CPU,just a behavioral model is not enought,
and i should consentrate on the RTL model .right?
: )

All behaviral models must be there for your to use. Especially they are
compiled in a function or a procedure form and incooperated in
synthesizer. If they are not ready, they are not available and you
cannot use it.

For example, when you multiply 2 16-bit integers, by using the
behaviral model, what you need to do is to write
C <= A*B; if they are defined properly. You don't have to care how it
is implemented in details.

And the synthizer will generate code for you. There is a liberary that
does it for you.

The library may be working, but not in the most efficient form.

For your situation as a beginner, that you start with behaviral model
is appropriate.

All behaviral models, if they pass the compilation, can be synthesized
without any problem.

Weng

Hello,

Weng Tianxiang schrieb:
> For your situation as a beginner, that you start with behaviral model
> is appropriate.
>
> All behaviral models, if they pass the compilation, can be synthesized
> without any problem.

I disagree. Behavioral means you describe what to do on a abstract
level. This might be synthesisable but is not allways synthesisable. In
fact behavioral means you didn't care, if its synthesisable. There
exist tools to help you synthesising behavioral code, but they are
limited.

out<=a+b;

is behavioral[1], but synthesisable with every tool, if a and b are
integer or std_logic_vector. The code is hardly synthesisabel if a and
b are complex type useing a special function for "+".

The following behavioral model would pass every compilation but could
never be sythesised:

var a, b : integer
for i in 1 to 10 loop
a := a *b;
b := b+i;
end loop
wait for 1 us;

bye Thomas

[1] and is also accepted as rtl code for integer or std_logic_vector.

I agree with your this opinion:
"Behavioral means you describe what to do on a abstract level."

I like saying that in another way as a everyday life thing:
Behaviral means something other people have already help build, either
in a library or in a module.

If they are available, they are synthesisable, otherwise they are not.

Here is the function to do complex addition in IEEE Standard VHDL
Mathematical Packages
function "+" ( L: in COMPLEX; R: in COMPLEX ) return COMPLEX;

Weng

Actually I started using VHDL about 6 years ago. As a starter, I was
really confused with the behavioral and RTL model definitions. Later I
learned that you don't have to understand it and can safely put it
aside without any harm. Even their concepts are not only useless, but
also harmful and meaningless.

Do you hear the same things in software? No. it is not because the same
things don't happen with software, but because in software industry, no
body talks about the concept. When you call a subroutine in software,
in VHDL, it is called behavioral, when you design it with assembly
language, in VHDL, it is called RTL.

When you hold a party, do you really care the dishes are made by
yourselves or by order?

The decisive thing about a code is that it is reliable and error free.

Every beginner with VHDL or Verilog has to face the same dillema: what
are the behavioral and RTL model definitions?

Weng