«

I've created a type which is an array (63 downto 0) of std_logic_vector(15
downto 0).

Then I make a signal assigment like this:

Dest_sig <= Sourc_sig;

Both signals are of the type I described above.

The problem is that Dest_sig doesn't seem to get the desired values...

Maybe the problem is that I cannot assign such big signals? Should I loop
component by component?

Thanls,

"Xin Xiao" <> wrote in message
news:fl9768$d26$...
> I've created a type which is an array (63 downto 0) of std_logic_vector(15
> downto 0).
>
> Then I make a signal assigment like this:
>
> Dest_sig <= Sourc_sig;
>
> Both signals are of the type I described above.
>
> The problem is that Dest_sig doesn't seem to get the desired values...
>
> Maybe the problem is that I cannot assign such big signals? Should I loop
> component by component?
>
> Thanls,

Hi,

Your statement is perfectly valid and shouldn't cause any troubles by
itself. You should tell us more of what you're seeing and expecting and give
a bit of the code surrounding this statement.

Regards,
Alvin.

i think it is working now. i'm happy.

i think the problem was dest_sig. it was an inout port, so i divided it into
two in and out ports and it's working.

i'm investigating this further maybe i missed something...

thanks

"Alvin Andries" <> wrote in
message news:47782430$0$18792$...
>
> "Xin Xiao" <> wrote in message
> news:fl9768$d26$...
>> I've created a type which is an array (63 downto 0) of
>> std_logic_vector(15
>> downto 0).
>>
>> Then I make a signal assigment like this:
>>
>> Dest_sig <= Sourc_sig;
>>
>> Both signals are of the type I described above.
>>
>> The problem is that Dest_sig doesn't seem to get the desired values...
>>
>> Maybe the problem is that I cannot assign such big signals? Should I loop
>> component by component?
>>
>> Thanls,
>
> Hi,
>
> Your statement is perfectly valid and shouldn't cause any troubles by
> itself. You should tell us more of what you're seeing and expecting and
> give
> a bit of the code surrounding this statement.
>
> Regards,
> Alvin.
>
>

"Xin Xiao" <> wrote in message
news:fl9768$d26$...
> I've created a type which is an array (63 downto 0) of std_logic_vector(15
> downto 0).
>
> Then I make a signal assigment like this:
>
> Dest_sig <= Sourc_sig;
>
> Both signals are of the type I described above.
>
> The problem is that Dest_sig doesn't seem to get the desired values...
>
> Maybe the problem is that I cannot assign such big signals? Should I loop
> component by component?
>
> Thanls,

What you've described is fine. Post your code and what exactly you think is
not correct and what sim tool you're using.

KJ

thanks kj, the problam was that dest_sig was an inout port. I divided into
in and out ports and it's working now. is my problem a common mistake that
happen with inout ports?

What i saw is that the port was full of 'U's, not the 0's of Source_sig.

"KJ" <> wrote in message
news:98Wdj.214$.. .
>
> "Xin Xiao" <> wrote in message
> news:fl9768$d26$...
>> I've created a type which is an array (63 downto 0) of
>> std_logic_vector(15 downto 0).
>>
>> Then I make a signal assigment like this:
>>
>> Dest_sig <= Sourc_sig;
>>
>> Both signals are of the type I described above.
>>
>> The problem is that Dest_sig doesn't seem to get the desired values...
>>
>> Maybe the problem is that I cannot assign such big signals? Should I loop
>> component by component?
>>
>> Thanls,
>
> What you've described is fine. Post your code and what exactly you think
> is not correct and what sim tool you're using.
>
> KJ
>

"Xin Xiao" <> wrote in message
news:fl9b6v$m9o$...
> thanks kj, the problam was that dest_sig was an inout port. I divided into
> in and out ports and it's working now. is my problem a common mistake that
> happen with inout ports?

Can't really say since you didn't post any code to look at. By itself,
driving an inout is not a problem, but I suspect that the way you were using
the port caused the signal to drive to loop back and drive itself which
would cause it to be unable to get out of the 'U' state since 'U' trumps
everything.

>
> What i saw is that the port was full of 'U's, not the 0's of Source_sig.
>
'U' is what you'll get if there is some driver on the net that is undriven
(the 'U' means uninitialized, which is the default for any signal that is
not explicitly initialized in the code somewhere).

KJ

On Mon, 31 Dec 2007 00:48:22 +0100, "Xin Xiao" <> wrote:

>
>i think it is working now. i'm happy.
>
>i think the problem was dest_sig. it was an inout port, so i divided it into
>two in and out ports and it's working.

And that may be the solution to your problem.

>i'm investigating this further maybe i missed something...
>
Having got it working with separate ports, you may want to go back and
learn how to do it with an Inout port.

If Source is outside the unit with the port, driving IN to the port, you
have to remember that the unit is also driving OUT on the same port, and
the result is the combination of both those signals according to the
resolution function.

So, to drive IN, you have to make sure the unit drives
(others =>(others=>'Z')) onto the port. In other words it turns its own
drivers OFF to allow the external signal in.

And to drive out from the port, you will have to drive 'Z' into it, from
your external source.

Also bear in mind that internal signals in FPGAs are best implemented as
separate In and Out ports, because tristate drivers (capable of driving
'Z') no longer exist in modern FPGAs. The logic will still work; but the
tools will effectively replace the tristate drivers with logic gates.

The place you need to use InOut ports is external signals, e.g. to
memory or processors or other FPGAs connected to your FPGA.

- Brian