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VHDL design hierarchy, modules/componets and I/O pins

Mike Treseler

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Posts: n/a

03-09-2006

Rafal Pietrak wrote:

> Yes. There will come time for that.

When the time comes, here's a starting point:
http://groups.google.com/groups/sear...hell+test_uart

> But I assure you, that I know what I'm doing regarding the learning path.

Do whatever the prof says to get a good grade,
but it seem to have little to do with
learning vhdl.

-- Mike Treseler

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