Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Enumeration types and bits

Reply
Thread Tools

Enumeration types and bits

 
 
Pleg
Guest
Posts: n/a
 
      03-07-2006
Let's say I've a proto board with a button; I don't know now if the wire
connected to the button has a value of 1 when the button is high or when
it's low, but I don't care: I'm using an enumerated type inside my VHDL
code: "type button_state is (high, low);". But now I want to map that states
"high", "low" to real "1", "0" so that I can use that button, linking it to
my signals in the .ucf file.
How do I do it? How can I map my enumerated type to binary 1,0s?


Thanks,


Pleg


 
Reply With Quote
 
 
 
 
Mike Treseler
Guest
Posts: n/a
 
      03-07-2006
Pleg wrote:

> How do I do it? How can I map my enumerated type to binary 1,0s?


An std_ulogic bit might be a better choice in this case.
I only use an enumerated type for internal registers
when I don't care what what values synthesis picks for me.

For example, with this code

type TxState_t is (
IDLE,
START,
SEND,
STOP
);
variable TxState_v : TxState_t;

I don't care if START becomes "01" "10" or "0001"
as long as synthesis decodes it consistently.
(it does)

-- Mike Treseler
 
Reply With Quote
 
 
 
 
Pleg
Guest
Posts: n/a
 
      03-07-2006
> An std_ulogic bit might be a better choice in this case.
> I only use an enumerated type for internal registers
> when I don't care what what values synthesis picks for me.


Yes I was afraid that the answer was something like this

Thanks!



Pleg


 
Reply With Quote
 
Rob Dekker
Guest
Posts: n/a
 
      03-08-2006
Hi Pleg,

Most synthesis tools support the attribute ENUM_ENCODING for this.
It allows you to set the bit-encoding for the values of an enumerated type.

For two states, that (encoding) is sort of a no-oops, but for more states it
can and will make a difference (good or bad).

Also note that synthesis tools choose a 'default' encoding scheme if you do
not specify the enum_encoding attribute. The default differs per tool, and
sometimes per target technology. FPGA synthesis tools often default to onehot encoding,
while default 'binary' encoding is standard practice for ASICs.

Rob


"Pleg" <(E-Mail Removed)> wrote in message news:fzmPf.20492$(E-Mail Removed).. .
> Let's say I've a proto board with a button; I don't know now if the wire
> connected to the button has a value of 1 when the button is high or when
> it's low, but I don't care: I'm using an enumerated type inside my VHDL
> code: "type button_state is (high, low);". But now I want to map that states
> "high", "low" to real "1", "0" so that I can use that button, linking it to
> my signals in the .ucf file.
> How do I do it? How can I map my enumerated type to binary 1,0s?
>
>
> Thanks,
>
>
> Pleg
>
>



 
Reply With Quote
 
Pleg
Guest
Posts: n/a
 
      03-10-2006
Thanks to everybody!


Pleg


 
Reply With Quote
 
KJ
Guest
Posts: n/a
 
      03-10-2006
You can convert the std_logic to an integer and then use that as an input to
the 'val attribute. Something like the code below (code is not totally
correct, but should be close enough for you to work out the details).

entity Top is....
Button: std_logic;
end Top;

architecture RTL of Top is
type button_state is (high, low);
signal Button_Signal, Button_Signal2: button_state;

-- Maybe make a function to do the conversion from std_logic to button
type....hides the details of the conversion
-- when you go to use it....on the other hand, this function probably
only gets used in one place of the code anyway
--
function To_Button_State(L: std_logic) return button_state is
variable RetVal: button_state;
begin
RetVal := button_state'val(to_integer(unsigned(L)));
return(RetVal);
end To_Button_State;
begin
-- Some like to see a simple type conversion function being called in
the 'main' VHDL
Button_Signal <= To_Button_State(Button);

-- Or alternatively you could use....
Button_Signal2 <= button_state'val(to_integer(unsigned(Button)));
end RTL;

"Pleg" <(E-Mail Removed)> wrote in message
news:fzmPf.20492$(E-Mail Removed).. .
> Let's say I've a proto board with a button; I don't know now if the wire
> connected to the button has a value of 1 when the button is high or when
> it's low, but I don't care: I'm using an enumerated type inside my VHDL
> code: "type button_state is (high, low);". But now I want to map that
> states
> "high", "low" to real "1", "0" so that I can use that button, linking it
> to
> my signals in the .ucf file.
> How do I do it? How can I map my enumerated type to binary 1,0s?
>
>
> Thanks,
>
>
> Pleg
>
>



 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Extend enumeration types? Marcel Müller C++ 4 09-14-2009 09:01 AM
Re-using a simple type definition; with enumeration constraint andwithout enumeration constraint puvit82 XML 4 02-01-2008 03:46 PM
Generating Enumeration Types at runtime Markus Schickler Java 5 06-09-2007 06:09 PM
enumeration types Charlie VHDL 4 02-09-2005 03:01 PM
8-Bits vs 12 or 16 bits/pixel; When does more than 8 bits count ? Al Dykes Digital Photography 3 12-29-2003 07:08 PM



Advertisments